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Fig. 2 | Nanoscale Research Letters

Fig. 2

From: Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Fig. 2

a The proposed structure of GAA nanosheet FATFET and b its 2D view along the Z-cut, showing device specifications, regions, and location of area tunneling. An n-epitaxial region surrounds the overlapped source (\(L_{{\rm sov}}\)) and channel regions to achieve complete area of tunneling. c The simplified processing mechanisms for the proposed geometry based on recent inventions

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