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Table 2 Chip-level parameters and performances computed per epoch for the GeOx ReRAM synapse array-based PIM architecture

From: Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

PIM chip parameters

Values

Chip area

62.5 mm2

Total energy on chip

3.35 × 10–5 J

Latency

1.33 ms

Peak energy efficiency

58.92 TOPS/W

Mean energy efficiency

36.42 TOPS/W

Inference energy in the synapse array

1.64 × 10–6 J

Other logic energy

3.55 × 10–7 J

ADC energy

1.37 × 10–5 J

Interconnect energy

1.20 × 10–5 J

Inference latency in the synapse array

2.20 × 10–5 s

Other logic latency

5.58 × 10–4 s

ADC latency

5.86 × 10–5 s

Interconnect latency

5.55 × 10–4 s

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