Fig. 7
From: Large Dense Periodic Arrays of Vertically Aligned Sharp Silicon Nanocones
A top-view schematic representation of a 100-mm-diameter silicon substrate map is shown in the top-left corner. The black rectangular boxes indicate the SiNC arrays (size 1.5 × 4 mm2) on the substrate where the SiNC arrays are present. Two dotted lines show examples of the locations where the cleaving planes are supposed to intersect the nanocone arrays. Cross-sectional SEM images displayed in this figure were recorded at the cleaving planes, showing SiNC arrays fabricated at oxidation temperatures of 850, 900, and 950 °C and recorded at different locations. Height measurements of the coated and stripped SiNC arrays are conducted, as shown in (850 °C; C; (3,2)). The scale bars represent 100 nm