Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.


Background
Memristors are being intensively explored as possible candidate for future memories because of simplicity in fabrication, possibility in three-dimensional integration, compatibility with (complementary metal-oxidesemiconductor) CMOS technology in the fabrication process, and so on. However, real integration of memristors and CMOS circuits is very rarely available to most engineers and scholars who want to be involved in designing various kinds of CMOS circuits using memristors. To help those engineers and scholars who cannot access memristor fabrication technology but want to design memristor circuits, a CMOS emulator circuit that can reproduce the physical hysteresis loop of memristor's voltage-current relationship is needed.

Methods
Before we develop a CMOS emulator circuit for memristor, memristive behavior should be explained first. The following simple equation (Equation 1) can describe the memristor's current-voltage relationship [1,2]: Here v(t) and i(t) represent the voltage and current of memristor, respectively. R X (t) is the memristance that changes with respect to time. R SET and R RESET are SET and RESET resistance, respectively. w(t) is the effective width of the memristor. D is the total drift length of w(t). q(t) is an accumulated charge flow through the memristor. Q CRIT means an amount of critical charge to RESET-to-SET transition. When q(t) becomes equal to Q CRIT , R X (t) is changed to R SET from R RESET . Here μ v is the mobility of dopant in Equation 1 [1,2].
To describe the memristive behavior that follows the relationship of current and voltage in Equation 1, a few emulator circuits have already been proposed [3][4][5].
Pershin and Ventra proposed an emulator circuit that is composed of an analog-to-digital converter and microcontroller that are implemented by discrete off-chip devices. Thus, they can be considered too much complicated and too large to be integrated in a single chip [3]. Jung et al. proposed an emulator circuit that is based on CMOS technology [4], where a memristor that should change its resistance in response to the applied current and voltage is implemented by an array of resistors. In the emulator circuit with resistor array, the analog-to-digital converter and the decoder circuit select a proper resistor among many resistors that are placed in the resistor array according to the applied voltage or current [4]. One problem in the emulator circuit [4] is that the voltagecurrent relationship seems sawtooth. This is because the resolution of memristance change is decided by the resolution of the analog-to-digital converter, as you see in [4]. If we have 4-bit analog-to-digital converter in the emulator circuit, it means that only 16 values of memristance are available. As a result, when we apply a voltage that is a sinusoidal function to the memristor, we can know that its current is increased or decreased like sawtooth. To improve the resolution of memristance change, the resolution of the analog-to-digital converter should be increased too. If the resolution of the analogto-digital converter is improved from 4 to 5 bit, the voltage-current relationship of the emulator circuit with 5 bit seems to be much finer than the emulator circuit with a 4-bit analog-to-digital converter, as shown in [4]. To improve the resolution twice, however, the number of resistors in the resistor array should be double too. It can cause a large area overhead in realizing this emulator circuit in a single chip. Especially, in implementing memristor array with this emulator circuit, this large area overhead of each memristor emulator cell can be a serious problem because each cell in the memristor array should be realized by this large-area single memristor emulator.
To mitigate the large area overhead of the previous emulator circuit, we propose a new emulator circuit of memristors that is more compact and simpler than the previous emulator circuits [6]. The new emulator circuit does not use a resistor array, an analog-to-digital converter, and so on that usually occupy very large area. Instead of using the complicated circuit blocks that were mentioned just earlier, the new circuit can change its memristance value by a simple voltage-controlled resistor that can be realized by a single n-type metal-oxidesemiconductor field-effect transistor (NMOSFET) device.

Newly proposed emulator circuit for describing memristive behavior
A schematic of the proposed emulator circuit for describing memristive behavior is shown in Figure 1. The CMOS circuit for emulating memristive behavior is composed of transmission gates, comparators, current mirrors, voltagecontrolled resistor, etc. as shown in Figure 1. V IN is an input voltage source and V IN+ and V IN− represent the anode and cathode of the input voltage source, respectively. In Figure 1, V IN+ is connected to TG 1 and TG 2 that are controlled by T B and T, respectively. Similarly, V IN− is connected to TG 3 and TG 4 that are controlled by T and T B , respectively. When V IN+ is greater than V IN− , T becomes high and T B becomes low, by the comparator G 1 . On the contrary, when V IN+ is smaller than V IN− , T becomes low and T B becomes high. Thus, we can know that V IN+ is connected to V A through TG 2 when V IN+ is larger than V IN− . At the same moment, V IN− is connected to the ground potential (GND) by TG 3 4 , and V IN+ is biased by GND through TG 1 . One thing to note here is that we can deliver the input voltage V IN to V A without any sacrificial voltage loss, using the transmission gate. The V IN delivering block that is composed of four transmission gates, TG 1 , TG 2 , TG 3 , and TG 4 , can deliver V IN+ and V IN− that are plus and minus polarity of V IN , respectively, to V A that has only plus polarity, not minus. The delivered voltage V A is copied exactly to V B by the negative feedback circuit that is composed of the OP amp, G 2 , M 3 , and M 4 . Using this circuit block, V B can be the same as V A by the feedback amplifier with unity gain. V B is connected to the voltage-controlled resistor M 2 that is controlled by V C . One more thing to note here is that V C controls both voltage-controlled resistors M 1 and M 2 that are electrically isolated from each other. By doing so, we can separate the memristor's current from the programming current to change the state variable that is stored at the capacitor C 1 . If the memristor's current is not separated from the programming current, the state variable that decides memristance value can be maintained only at the moment when the programming voltage or current is applied to the memristor. If so, the emulator circuit cannot keep its  programmed state variable when the applied voltage or current is removed. V C that controls two voltage-controlled resistors M 1 and M 2 acts as a state variable in the emulator circuit that is calculated by an amount of stored charge at C 1 . When V IN+ is greater than V IN− , TG 7 is on and both TG 5 and TG 6 are off. At this time, the current mirror that is composed of M 5 and M 6 delivers the programming current to C 1 to increase an amount of stored charge; thereby the state variable becomes larger. On the other hand, when V IN− is greater than V IN+ , TG 7 is off and both TG 5 and TG 6 are on. By doing so, we can decrease the amount of charge that is stored at the state variable capacitorC 1 . The discharging current path is composed of M 7 , M 8 , M 9 , and M 10 in Figure 1. Here V BN and V BP are the biasing voltages for NMOSFETs and PMOSFETs, respectively. V BN and V BP are made from the biasing circuit that is shown in Figure 1. D 1 , D 2 , and D 3 are the diodes that are used in the proposed emulator circuit to limit the minimum value of V C . This minimum value of V C is needed to avoid the dead zone which may be caused by the sub-threshold region of the voltage-controlled resistors M 1 and M 2 . V D means the diode voltage of D 1 , D 2 , and D 3 . V DD is the power supply voltage of the CMOS emulator circuit in Figure 1.
One more thing to consider here is that the nonlinearity of memristive behaviors can be found when the effective width of memristor, w(t), in Equation 1 becomes much closer to the boundary constraints [1,7]. This nonlinearity near the boundary values of w(t) was introduced in the HP model [1] and mathematically modeled by Corinto and Ascoli [7] to describe various nonlinear behaviors of memristors. In terms of implementation, the diode bridge circuit with LCR filter was proposed to reproduce memristive nature with nonlinearity by using a very simple electronic circuit [8]. In this paper, the window function that is used to define two boundary values of the state variable in the HP model [1] is realized in the CMOS emulator circuit that is shown in Figure 1. The emulator circuit in Figure 1 has two boundary values of the state variable that is defined by V C . Here we can know that the maximum value of V C cannot exceed V DD . And also, V C cannot be lower than V DD -3V D . Thus, the state variable of V C in Figure 1 can exist only between V DD and V DD -3V D , not being higher than V DD and lower than V DD -3V D , respectively.  Figure 1 is shown in Figure 2b. As the sinusoidal voltage is applied to the emulator circuit in Figure 1, I IN changes with respect to time according to the state variable that is represented by V C , the amount of stored charge at C 1 . When V C has the lowest value, it means that the state variable is in RESET state, where the emulator circuit acts like a memristor with RESET resistance. After the half cycle of sinusoidal function, V C is charged more and more; thereby V C can reach the highest value. With the highest value of V C , the state variable can be in SET state, where the emulator circuit can be considered a SET resistance. Figure 2c shows the voltage waveform of V C with respect to time. At the starting point of sinusoidal function of V IN , V C is 1.2 V that is decided by D 1 in Figure 1. After the half cycle of sinusoidal function, V C reaches 2.8 V. When one cycle of sinusoidal function is completed, the V C value returns to the value at the starting point of sinusoidal function. Figure 2d shows a typical pinched hysteresis loop of a memristor's voltage and current which are emulated by the proposed circuit in Figure 1. In the simulation, V DD is 3.3 V and the frequency of sinusoidal function is 10 kHz.

Results and discussion
Figure 2e, f, g, h shows the simulation results of the proposed emulator circuit with four times higher frequency of 40 kHz than that of Figure 2a, b, c, d, V IN , I IN , V C , and the pinched hysteresis loop, respectively, with 10 kHz. A sinusoidal voltage with 40 kHz that is applied to the emulator circuit is shown in Figure 2e. Here the first three peaks are for increasing V C in Figure 1; thereby, the emulator circuit changes from RESET to SET. The next three peaks are for decreasing the state variable; thus, the emulator circuit can return to RESET. I IN and V C with the sinusoidal function that is indicated in Figure 2e  shown in Figure 2f, g, respectively. Figure 2h shows the voltage-current relationship of the emulator circuit. In Figure 2h we can see three voltage-current loops at the right and another three voltage-current loops at the left which correspond to the three high peaks and three low peaks in Figure 2e, respectively. Figure 3a shows SET pulses with different amplitude values. Here the amplitude values are increasing monotonically from 0.5 to 3 V. Each SET pulse is followed by a RESET pulse with the fixed amplitude as high as 3 V that is shown in Figure 3b. The state variable that is changed by SET and RESET pulses are shown in Figure 3c. Here V C represents the amount of stored charge at C 1 that controls the voltage-controlled resistor in Figure 1 that acts as memristor. Figure 4a shows the read and write circuits for the proposed emulator circuit of memristors [9,10]. The read circuit is simply composed of a current mirror and comparator. The comparator G 1 compares the sensing voltage V SEN with the reference voltage V REF . The sensing voltage V SEN can change according to the programmed memristance value of the emulator circuit. If the state variable is closer to RESET, the sensing voltage V SEN becomes larger due to a large value of memristance. On the contrary, the state variable is in SET, and V SEN is smaller than V REF . Here D OUT is the output voltage of the read circuit. G 2 is the inverter for RD that is the 'read' command signal. TG 1 and TG 2 are the transmission gates for the read operation. When RD is high, TG 1 and TG 2 are on. On the contrary, TG 3 and TG 4 are on for the 'write' operation that is activated by the write command signal WR. The input data D IN drives the inverter G 3 . And G 3 drives the next inverter G 4 . The anode and cathode of the proposed emulator circuit are driven by the two inverters, G 3 and G 4 , respectively. Figure 4b shows the voltage waveforms of D IN , WR, RD, and D OUT . Figure 5 compares the layout area of the previous emulator circuit [4] and the proposed emulator circuit.
Because the resistor array is not used in the proposed circuit and the analog-to-digital converter and decoder are eliminated in this paper, the layout area of the previous emulator circuit is estimated to be 32 times larger than the emulator circuit proposed in this paper. The design rule used in this layout is MagnaChip 0.35-μm technology.

Conclusions
In this paper, a CMOS circuit that could emulate memristive behavior was proposed. The proposed emulator circuit could mimic the pinched hysteresis loops of a memristor's current-voltage relationship without using a resistor array and complicated circuit blocks that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit could mimic memristive behavior using simple voltage-controlled resistors, where the resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the emulator circuit proposed in this paper was estimated to be 32 times smaller than the previous emulator circuit.