Influence of post-annealing on the off current of MoS2 field-effect transistors

Two-dimensional materials have recently been spotlighted, due to their unique properties in comparison with conventional bulk and thin-film materials. Among those materials, MoS2 is one of the promising candidates for the active layer of electronic devices because it shows high electron mobility and pristine band gap. In this paper, we focus on the evolution of the electrical property of the MoS2 field-effect transistor (FET) as a function of post-annealing temperature. The results indicate that the off current drastically decreased at 200°C and increased at 400°C while other factors, such as the mobility and threshold voltage, show little variation. We consider that the decreasing off current comes from the rearrangement of the MoS2 film and the elimination of the surface residue. Then, the increasing off current was caused by the change of the material's composition and adsorption of H2O and O2. Electronic supplementary material The online version of this article (doi:10.1186/s11671-015-0773-y) contains supplementary material, which is available to authorized users.

Though engineering a band gap of graphene can be an answer for this technical issue, it increases the number of fabrication steps [18,19] and reduces the electron mobility of graphene [20]. As an alternative, MoS 2 has an intrinsic band gap, which leads to reduced off current. For example, MoS 2 FETs have in general recorded an on/off current ratio of 10 5~1 0 10 [21][22][23][24][25][26][27][28], and some MoS 2 FETs with high-k dielectrics have recorded an electron mobility of 200 cm 2 /Vs, which is higher than that of band gap-engineered graphene [21].
Many reports have announced that the annealing process is dispensable for improving the electrical property of various FETs using original IV semiconductors [29], oxide semiconductors [30,31], layered semiconductors [32][33][34], etc. In the case of 4H-SiC included in the original IV, the annealing process created a passivation layer at the interface, and device parameters were improved, such as the electron mobility and subthreshold swing (SS). In the case of InGaZnO included in oxide semiconductors, the annealing process rearranged defects, and all the device parameters improved, such as V th , SS, mobility, hysteresis, and the on/off current ratio. For graphene included in a layered material, the annealing process eliminated the resist residue on the surface and increased conductance.
For MoS 2 , a few results have been reported from the viewpoint of the post-annealing process [21,23,26]. One paper showed variation in the optical property, by observing the change of the photoluminescence (PL) peak of single-layer MoS 2 with respect to post-annealing [35]. Although it did not evaluate the electrical property of FETs, it reported that the annealing process induced structural rearrangement, and this could also affect the electrical properties of MoS 2 . Another paper investigated the influence of vacuum annealing on MoS 2 FET during measurement of the electrical property [22]. It announced a drastic improvement of electrical performance by annealing, especially in the conductance of the device. However, it focused on the electrical characteristics caused by movement of carriers at elevated temperature, which consequently present the thermally activated characteristics of MoS 2 FET. Here, we summarize the evolution of the electrical performance of MoS 2 FET at room temperature, which is the conventional operating temperature, with various postannealing temperatures.

Methods
MoS 2 flakes were prepared using a scotch-tape micromechanical cleavage technique, from bulk MoS 2 crystal (429ML-AB, SPI Supplies, Inc., West Chester, PA, USA), and were transferred to highly doped silicon substrates covered with 300-nm-thick SiO 2 . Source and drain (S/D) were patterned by photolithography, and 50-nm-thick Ti was deposited by an e-beam evaporator. Then, a conventional lift-off process was accomplished for the patterning of the S/D electrode. The fabricated MoS 2 FET was annealed in a nitrogen environment for 2 h at various temperatures. The electrical characteristic was measured under atmospheric pressure at room temperature. Furthermore, the thicknesses of the MoS 2 flakes were measured using atomic force microscopy (AFM; XE-100, Park Systems, Suwon, South Korea). Figure 1a is a schematic diagram of the MoS 2 FET, and Figure 1b is an AFM profile that corresponds to the red line of the MoS 2 image from the inset. The thickness of the MoS 2 channel measured by AFM was 11 nm. While there has been controversy over whether using a single-layer MoS 2 channel is a requirement for getting higher device performance, some papers proved that a multilayer MoS 2 channel was also able to attain comparable device performance, such as a high electron mobility over 100 cm 2 /Vs and a high on/off current ratio of over 10 6 [23,36]. Therefore, it is thought that the performance of the multilayer MoS 2 is sufficient to study the post-annealing effect. Figure 2 shows the representative I d -V g characteristics under constant V d = 10 V, with respect to the postannealing temperature among the many multilayer MoS 2 FETs shown in Additional file 1: Figure S1. This representative flake has a channel length of 10 μm and a width of 20 μm. This represents the n-type nature of the MoS 2 channel that makes the accumulation layer of electrons at positive gate biases, and it is observed as increasing the drain current at positive gate biases.  Theoretically, the drain current is supposed to be below 10 −9 A at high negative gate biases, due to a depletion layer; however, a drain current of over 10 −5 A was observed with various gate biases at room temperature (black line) and at 400°C (pink line). The drain current at the high negative gate biases drastically decreased by approximately 10 6 , compared to that of the device under room temperature, and it seemed that MoS 2 has a depletion layer at both 200°C (red line) and 300°C (blue line).

Results and discussion
In Figure 3a, the aforementioned transfer curves are arranged in terms of on and off current, with respect to post-annealing temperatures. The on current was defined as the highest drain current measured at high positive gate biases, and the off current was defined as the lowest drain current recorded at low negative gate biases. Figure 3a shows that the on current consistently decreases as the post-annealing temperature increases, while the off current decreases up to 200°C and increases with further increase of temperature. The lowest value of the off current was observed as approximately 10 −11 A for the 200°C-annealed device, and this trend is in line with the transfer curve characteristics. Figure 3b elaborates the field-effect mobility, which increased as the temperature rose and reached a high value of approximately 20.7 cm 2 /Vs at 200°C and 300°C. The field-effect mobility with respect to the postannealing temperature is also in accordance with the trend of the off current. Table 1 summarizes the details of the FET device performance parameters as annealing temperature.
Under those trends, the status of the device can be categorized into two regions. The first region, here termed region I, is that in which the device performance improves from room temperature to 200°C with decreasing off current and increasing field-effect mobility. The second region (region II) is that in which the device performance degrades from 200°C to 400°C with increasing off current and decreasing field-effect mobility.
In region I, the decrease of off current is thought to be caused by the atomic arrangement of MoS 2 atoms in local sites due to thermal energy. This kind of internal structural modification ends up with the release of a native point defect at the interface between the insulator and the channel material [30]. The interface properties between the MoS 2 and SiO 2 seemed to be improved, in that the subthreshold swing decreased from 36.20 to 0.91 [V/dec], as the post-annealing temperature increased to 200°C.  Exact values of the on/off current ratio, on current, off current, subthreshold swing, and field-effect mobility, at different temperatures.
Also, it is thought that the resist residue included during the fabrication process might be eliminated by the post-annealing process. The photoresist and organic materials from the 3M tape (3M, St. Paul, MN, USA) are one of the plausible candidates to be eliminated, and specifically, elimination of the photoresist residue of the graphene FET was observed with improvement of the device performance during the post-annealing process [33].
In region II, as mentioned, an increase of the off current by 5 or 6 orders was measured.
First, it is thought that such huge increase is caused by the change of the channel material itself. This is supported by the case of oxide semiconductors, such as InGaZnO 4 where desorption of Zn and O atoms over 700°C annealing and degradation in device performance were observed [30]. Similarly, the results of the X-ray photoelectron spectroscopy (XPS) proved that the S to Mo composition ratio significantly increased after annealing at 400°C in N 2 (Table 2). Furthermore, time-of-flight secondary ion mass spectroscopy (TOF-SIMS) depth profiles in Additional file 1: Figure S2 show that Mo decreased after annealing at 400°C in N 2 , which correlated with the XPS data.
From Figure 4, Mo 3d 5/2 and S 2p 3/2 peaks were shifted in a higher energy by 0.6 and 0.5 eV, respectively, after annealing at 400°C. The molybdenum peak shift means that Mo 4+ (228.98 eV) was changed into Mo 5+ (230.3 eV) [37], and the S 2p 3/2 peak shift toward a high binding energy (over 161.88 eV) has been ascribed to polysulfide or thiomolybdate species [38]. That is, one of the strong candidates for explaining the increase of the off current is the phase transformation of MoS 2 into Mo 2 S 5 [39] by thermal energy. Furthermore, previous literature [40] provided evidence for this changed form to have high off current in terms of resistivity.
From a different point of view, adsorption of H 2 O and O 2 on MoS 2 can also be one of the reasons for the increase of the off current. Under vacuum conditions, the off current actually decreased by average 10 2 level and this change is elaborated in Additional file 1: Figure S3. Therefore, it is guessed that adsorption was carried out after the high-temperature annealing process for the measurement of electrical characteristics at an atmosphere environment, and it was also supported by the case of graphene [41].

Conclusions
The evolution of off current for MoS 2 FET due to annealing temperature was systematically analyzed. As a result, the off current decreased up to 200°C annealing and increased for higher temperature annealing. Plausible explanations for the decrease in off current are the rearrangement of MoS 2 atoms and the elimination of the surface residue. Possible explanations for the increase in off current are the changes of the material's composition ratio and adsorption of H 2 O and O 2 . This research is meaningful in that the off current was controlled by the post-annealing temperature. Change of composition ratio between molybdenum and sulfur with respect to post-annealing.