Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.


Background
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) brings significant improvement in integrated circuit (IC) power consumption, switching characteristic, circuit function, and IC density [1,2]. But the irreconcilable contradiction between the scaling of the supply voltage and the reduction of the off-state leakage currents (I OFF ) will finally result in the unacceptable high power consumption [3]. At the same time, reliability degradation caused by short-channel effects (SCEs) becomes more and more serious [4,5]. In order to address these problems, it is valid to reduce subthreshold swing (SS) and supply voltage of the devices. Based on the band-to-band tunneling mechanism, tunnel field-effect transistors (TFETs) reach the subthreshold swing (SS) smaller than 60 mV/dec and could effectively reduce the supply voltage [6][7][8][9][10]. Moreover, due to the existence of the tunneling junction near the source, TFET usually has a small gate to source capacitance (C gs ) [1,11] which is beneficial to the device frequency performance.
Recent studies show that TFET seems to be a promising candidate for future low-power applications [12][13][14][15][16] and analog/RF applications [17][18][19]. However, due to the small effective tunneling area, the limited tunneling current becomes an inherent disadvantage in conventional P-I-N TFET, which leads to a low on-state operating current (I ON ). In order to improve the TFET performance, many new structures have been proposed in recent years [20][21][22][23][24][25]. Benefiting from the recessed gate, L-shape tunnel field-effect transistor (LTFET) [23,24] and U-shape tunnel field-effect transistor (UTFET) [25] have been proposed to obtain high I ON with a compact device structure. However, there is still much room for improvement in LTFET and UTFET and needs to spend more effort to study the analog/RF performance of these devices.
In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with dual source is put forward and studied by TCAD simulation. The designed TGTFET can double the tunneling junction area compared with LTFET and UTFET. The gate overlap introduced by the designed T-shape gate can enhance the band-to-band tunneling rate (BBT rate). The simulation results show that the proposed TGTFET gains a higher I ON (8.1 × 10 − 5 A/μm at V d = 1 V) than the LTFET and UTFET under the same condition. Both of the SS min (at V g = 0.1 V) and the SS avg (0~0.5 V V g ) of TGTFET are lower than 60 mV/dec (24.4 mV/dec and 51.5 mV/dec, respectively). TGTFET gains better input/output characteristic (g m = 232 μS/μm, g ds = 214 μS/μm) than the UTFET and LTFET. Moreover, the capacitance characteristics of TGTFET, UTFET, and LTFET are discussed in detail. Finally, TGTFET gains better analog/RF performance (f T = 11.9 GHz and GBW = 2.3 GHz) compared to UTFET and LTFET. As a result, TGTFET with considerable good performance can be obtained.The structures of this paper are as follows: the "Methods" section includes the description of the structure and the parameters of TGTFET, LTFET [23,24], and UTFET [25] as well as the TCAD simulation methods. The "Results and Discussion" section includes the description of the simulation results. In this section, the mechanism, characteristic, and analog/RF performance of TGTFET are studied and compared with the LTFET and UTFET. The influence of the device parameters on TGTFET is analyzed in detail too. The "Conclusions" section gives a conclusion of this paper.

Methods
The structure of T-shape gate dual-source tunnel field-effect transistor (TGTFET) is illustrated in Fig. 1. The shape of the gate is similar to the alphabet letter "T" (green region). The dual-source regions are located on two sides of the gate (sapphire regions). Two n+ pockets (yellow regions) are inserted to increase the channel tunneling rate [20][21][22]. The n+ drain is placed in the bottom of the channel. Therefore, the T-shaped gate overlaps the n+ pockets in both the vertical and lateral directions. By this way, the electric field at the top of the tunneling junction can be increased. The electric field enhancement causes the energy band to bend more steeply. Finally, the electron tunneling rate is enhanced due to the corner electric field enhancement [26]. Figure 2 shows the device structure of LTFET [23,24], UTFET [25], and TGTFET. The gate overlap can help to enhance the tunneling efficiency of TGTFET. The dual-source regions in TGTFET can double the tunneling junction area compared with LTFET and UTFET.
Simulations of TGTFET, UTFET, and LTFET are carried out in Silvaco Atlas TCAD tools. Non-local BTBT model is introduced in this simulation to bring the energy band spatial variation into account, which can help to facilitate the accuracy of the BTBT tunneling process. Lombardi mobility model is considered to make the channel mobility more accurate (by considering the surface scattering including the transverse field and doping concentration). Fermi statistics and band gap narrowing model is taken into account to fit the effect of the highly doped regions. Shockley-Read-Hall recombination model is taken into account in this paper, too.

Results and Discussion
Device Mechanism and DC Characteristics with Different Parameters Figure 3a shows the transfer characteristics of the TGTFET with and without the gate overlap. With the additional gate overlap, the I ON increases from 7.5 × 10 −5 to 8.1 × 10 −5 A/μm at V g = V d = 1 V. Figure 3b shows the transfer characteristic curves of TGTFET, UTFET, and LTFET. In order to make the comparison more accurate, the simulation models and geometric dimensions of these three devices are set to be identical. As a result, the TGTFET has about a twofold increase in I ON compared with LTFET and UTFET, as shown in Fig. 3b. SS min of TGTFET is 24.4 mV/dec at V g = 0.1 V, and SS avg is 51.5 mV/dec when 0 V < V g < 0.5 V. The switching ratios (I ON /I OFF ) are 6.7 × 10 10 at V g = V d = 1 V and 6.5 × 10 8 at V g = V d = 0.5 V. Figure 4a, b shows the BBT rate of TGTFET with and without a 5-nm gate overlap. From Fig. 4c, we can clearly see that the device with a 5-nm gate overlap has a wider electron tunneling area under the device surface, which can lead to the I ON increasing. Figure 5a, b shows the 3D diagram of electric fields of TGTFET with and without gate overlap. Two electric field peaks appear in TGTFET with a 5-nm gate overlap, as shown in the dashed circle in Fig. 5a. No electric field peak appears in Fig. 5b attributed to the absences of the gate overlap. Figure 5c shows the energy band structure under the surface of the device. The inset in Fig. 5c shows the cut line location. With the gate overlap, a larger tunneling window can be obtained. Thus, a higher BBT rate and I ON can be achieved. Figure 6 shows the effects of n+ pocket on the performance of the TGTFET. The I OFF increases rapidly with the increasing of the n+ pocket doping concentration, as shown in Fig. 6a. The lower SS and greater I ON can be obtained by decreasing the thickness of n+ pocket (Tp) from 7 to 3 nm when N P = 5 × 10 18 cm −3 , as shown in Fig. 6b. At the same time, no significant subthreshold current is noted in Fig. 6b. It can be confirmed from Fig. 6a that a relatively low doping concentration of n+ pocket will help to suppress the subthreshold current.
The impact of the gate height (Hg) and channel thickness (Hc) is shown in Fig. 7a and SS improvement appears when Hg is increasing. Because when Hg = 35 nm, there is an obvious energy band hump on the on-state current path, becoming a certain obstacle to the lucky electrons (electrons which passed the tunneling junction), as shown in Fig. 7c, which can result in I on decrease. When Hg increases, the energy band hump is weakened, which cause the I ON and SS improvement. A slight I ON improvement is obtained with Hc decreasing, as shown in Fig. 7b. However, severe degradation on subthreshold characteristic can be observed when Hc decreases to 5 nm. This can be explained by the increasing subthreshold tunneling current at the corner of the n+ pocket, as shown in Fig. 8. Figure 8a shows the obvious off-state band-to-band tunneling phenomenon when Hc = 5 nm while Fig. 8b shows the I OFF current density when Hc = 5 nm. As shown in Fig. 9, the influence of drain to source voltage (V d ) is also taken into account in this paper. For V d < 0.6 V, I ON increases obviously with the increasing V d , as shown in Fig. 9a. This is explained by the fact that the potential of the p-channel is slowly growing in response to the increasing V d and results in the decreasing resistance of p-channel. For V d > 1.8 V, shown in Fig. 9b, the I ON almost does not increase with the increasing V d , but I OFF increases considerably. This is because of the subthreshold tunneling current at the corner of the n+ pocket increasing rapidly with the increasing V d . Finally, for 0.6 V < V d < 1.8 V, TGTFET exhibits good and stable performance. As a result, TGTFET is robust to drain-induced barrier lowering (DIBL) and exhibits a good and stable performance in a larger applied voltage dynamic range.
Analog/RF Performance of TGTFET, UTFET, and LTFET As a result, the maximum transconductance of TGTFET (232 μS/μm) is about two times larger than that of UTFET (120 μS/μm) and LTFET (110 μS/μm), as shown in Fig. 10. This is benefited from the current gain contributed by dual source and gate overlap. Figure 11 shows the output characteristics, output conductance (g ds ), and output impedance (R o ) curves of the TGTFET, UTFET, and LTFET. As shown in Fig. 11a,  it can be clearly seen that the output current of the device increases with the increase of V d , but when V d reaches above 0.6 V, the output current tends to saturate. Through observation, it is easy to find that the output current of TGTFET is two times larger than that of UTFET and LTFET. Figure 11b shows the output conductance (g ds ) and output impedance (R o ) curves of the TGTFET, UTFET, and LTFET. The g ds can be obtained through the derivation of the output current, as shown in Eq. (2) [27,29] while R o can be expressed as the reciprocal of the output conductance.
Due to the advantages on output current, TGTFET gains the highest g ds and the minimum R o of these three devices. Moreover, in Fig. 11, it is not difficult to find out that the linear region of the device output characteristics shows certain nonlinearity. As shown in Fig. 11a, R o decreases first and then increases with the increasing V d . Some research groups give the corresponding physical process about this phenomenon [7,30] but there are still some problems that have not been explained clearly. As we know, R o is determined by the resistance of channel region and tunneling junction. When V d < 0.4 V, R o decreases with the increasing V d . Consider the following situations, when V d = 0 V and V g = 1 V, none of the lucky electrons can be swept to the drain side, and almost all the electrons are trapped in the channel region by a relatively high drain barrier, as shown in the red dotted line frame in Fig. 12a, b. When 0 V < V d < 0.4 V, with the  Fig. 12b). Thus, the electrons trapped in the channel region can pass through the drain barrier and then be collected by drain. This is a thermal excitation process of electrons from channel to drain. Finally, as the tunneling junction has been completely turned on (when V g = 1 V), the tunneling current is always in a state of excess and the resistance introduced by tunneling junction can be ignored. At this time, R o is determined by the channel resistance and R o is decided by the electron thermal excitation process across the drain barrier. Thus, R o decreases with the increasing of V d . When V d > 0.6 V, these three devices gradually enter the saturation area and R o becomes larger. This is because when V d is large, almost all the electrons through the tunneling junction are swept to the drain side by the relatively high electric field. The tunneling current becomes the limit of the drain current. In this condition, R o is mainly determined by the tunneling junction. However, the tunneling efficiency cannot increase significantly while V d is increasing. V d has a small effect on the energy band structure of the tunneling junction (n+ pocket side), as shown in Fig. 12b. As a result, the tunneling current cannot increase obviously, and there is almost no I ON increase with the continually increasing V d (when V d > 0.6 V), which means an impedance increases. Moreover, when 0.4 V < V d < 0.6 V, R o is determined by both the channel resistance and tunneling junction.
It can be obtained from the above analysis that the R o of TFET is influenced by both the tunneling process and the channel electron thermal excitation process. The main physical mechanisms can dominate R o shifts with V d variation. Finally, the R o decreases first and then increases, thus causing the nonlinearity of the output characteristics. Incidentally, through the observation of Fig. 11b, it is easy to find that the output impedance of TGTFET is much smaller than that of the UTFET and LTFET. This is due to the better tunneling efficiency benefit from the dual-source and the lateral gate overlap structure of TGTFET. Figure 13 shows the energy band structure of TGTFET, UTFET, and LTFET with different applied voltages. The red dotted lines in the inset represent the position to draw the energy band (which is 15 nm below the surface, just at the 1/2 height of the source region). It can be seen that with a V d increase from 0.1 to 0.5 V, the band structure of TGTFET, UTFET, and LTFET has an obvious trend of bending. This is because the drain voltage can pull down the electric potential of the tunneling junction near the drain side. This indicates that, for TGTFET, UTFET, and LTFET, the increase of V d from 0.1 to 0.5 V is beneficial to tunneling efficiency. However, when V d > 0.5 V, the change of the energy band with V d increase is not worth mentioning. This is consistent with the analysis results in Fig. 12b.
As we know, the gate capacitance (C gg ) of the device can greatly affect the frequency characteristics of the integrated circuits. For TGTFET, UTFET, and LTFET, C gg generally consists of C gs (capacitance of gate to source) and C gd (gate to drain capacitance). Therefore, the characteristic of C gg , C gs , and C gd is of great significance to evaluate the frequency characteristics and analog application ability of devices. Especially for TFET, the capacitance characteristics are quite different from MOSFET. Because of the existence of the tunneling junction at the source area, TFET usually has a small C gs [1,11]. Therefore, the C gg of TFET is mainly determined by C gd . Figure 14 shows the capacitance of TGTFET, UTFET, and LTFET versus V g under V d = 0.5 V and V d = 0 V, separately.
Through the observation of Fig. 14a, b, it is easy to find that the C gs of TGTFET under 1-V gate voltage is 0.15 fF/μm at V d = 0 V and 0.7 fF/μm at V d = 0.5 V, which is far more smaller than that of the C gd (5.8 fF/ μm at V d = 0 V and 3.7 fF/μm at V d = 0.5 V). Thus, the C gg of TGTFET is mainly determined by C gd . When V d = 0 V, C gg and C gd increase rapidly with the increasing V g , as shown in Fig. 14a. This is because with the Fig. 13 The energy band structure of a TGTFET, b UTFET, and c LTFET at V g = 1 increase of V g , electrons are aggregated to the gate interface in the device channel, which makes the capacitance rise rapidly. When V d = 0.5 V, C gd does not increase obviously until V g is increased to more than 0.6 V, as shown in Fig. 14b. This is because when V g is low, only few lucky electrons can pass through the tunneling junction and go into the channel. Some of these lucky electrons will be participating in the recombination process, and most of the others will be rapidly collected by drain due to the 0.5-V drain voltage. Therefore, it is very difficult for these lucky electrons to stay in the device channel. However, with the V g increase, the number of lucky electrons increases rapidly. At this moment, neither of the drain collection nor of the electron-hole recombination process can rapidly deplete these lucky electrons. Thus, the electron concentration in the channel increases and the capacitance rises rapidly. As a result, the capacitance characteristic curve tends to shift right while V d increases, as shown in Fig. 14a, b. The above analysis and phenomena are also applicable to UTFET and LTFET, as shown in Fig. 14c-f. In addition, the gate capacitance of UTFET at 0 V and 0.5 V V d reached 6.2 fF/μm and 5.1 fF/μm, respectively, and that of the LTFET reached 3.4 fF/μm and 2.7 fF/μm, respectively.
Since there is no direct overlap between the LTFET's gate and drain, and the distance between the gate and drain is relatively far, LTFET has the best capacitance characteristics and the smallest C gg . In contrast, there is a direct overlap between the UTFET's gate and drain. Therefore, electrons near the drain side are more easily controlled by gate, thus resulting in a large C gg of UTFET. For TGTFET, although the distance between the gate and drain is close, but there is a lightly doped channel region which can isolate the gate and drain. Thus, the capacitance of TGTFET is better than that of the UTFET, but slightly inferior to LTFET. Figure 15 shows the C gd characteristics of TGTFET, UTFET, and LTFET versus V d under different V g . From the observation of Fig. 15a-v, it is not difficult to find that the C gd characteristics of these three devices are similar. That is, for a fixed V g , C gd decreases with the increase of the V d . On the other hand, for a fixed V d , C gd increases with the increase of V g .
As we know, both of the cut-off frequency (f T ) and gain bandwidth (GBW) are the evaluation criteria for evaluating the frequency characteristics of devices. f T depends on the ratio of g m to C gg , as shown in Eq. (3) [30,31]. For a certain DC gain that equals 10, GBW can be expressed by the ratio of g m to C gd , as shown in Eq. (4) [17]: Figure 16 shows the characteristic curves of the f T and GBW of TGTFET, UTFET, and LTFET. Benefiting from structural advantages, such as dual-source and lateral gate overlap introduced by the T-shaped gate, TGTFET obtains the most outstanding frequency characteristics compared with UTFET and LTFET. Under the condition of V d = 0.5 V, the f T and GBW of TGTFET reached the maximum values of 11.9 GHz and 2.3 GHz, respectively. Benefiting from the long distance between gate and drain and without gate/drain overlap, LTFET obtains a

Conclusions
In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with good performance is proposed and investigated. The structure, mechanism, and the influence of device parameter on the characteristic of TGTFET are discussed. In addition, the characteristics of TGTFET, UTFET, and LTFET are discussed and compared in this paper. The dual-source regions are introduced to double the area of the tunneling junction. The gate overlap and the n+ pockets can obviously enhance the tunneling efficiency of the tunneling junction in TGTFET. Finally, the TGTFET with impressive characteristics (I ON = 8.1 × 10 −5 A/μm, I ON /I OFF = 6.7 × 10 10 and SS min = 24.4 mV/dec) is obtained. At the same time, TGTFET is robust to DIBL, which means TGTFET can exhibit a good and stable performance in a larger applied voltage dynamic range. Furthermore, the analog/RF performance of TGTFET is studied and compared with UTFET and LTFET. The key parameter such as input/output characteristics, capacitance characteristics, GBW, and f T are analyzed. Benefiting from the no direct overlap between the gate and drain, TGTFET obtains a relatively small C gd and C gg . Finally, TGTFET with remarkable frequency characteristics (f T = 11.9 GHz and GBW = 2.3 GHz) is obtained. As a conclusion, it is expected that TGTFET can be one of the promising alternatives for the next generation of device in low-power and analog/RF applications.