High mobility Ge pMOSFETs with amorphous Si passivation: impact of surface orientation

We report the amorphous Si passivation of Ge pMOSFETs fabricated on (001)-, (011)-, and (111)-orientated surfaces for advanced CMOS and thin film transistor applications. Amorphous Si passivation of Ge is carried out by magnetron sputtering at room temperature. With the fixed thickness of Si tSi, (001)-oriented Ge pMOSFETs achieve the higher on-state current ION and effective hole mobility μeff compared to the devices on other orientations. At an inversion charge density Qinv of 3.5 × 1012 cm−2, Ge(001) transistors with 0.9 nm tSi demonstrate a peak μeff of 278 cm2/V × s, which is 2.97 times higher than the Si universal mobility. With the decreasing of tSi, ION of Ge transistors increases due to the reduction of capacitive effective thickness, but subthreshold swing and leakage floor characteristics are degraded attributed to the increasing of midgap Dit.


Background
Germanium (Ge) has been attracting tremendous research interests for advanced CMOS and thin film transistor applications due to its higher hole mobility and lower thermal budget processing compared to Si [1][2][3][4][5][6]. To achieve the high channel mobility, the surface passivation process leading to a high interface quality is required before gate stack formation. Several surface passivation techniques have been developed to deliver the carrier mobility benefits in Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) [1,2,[7][8][9][10]. Among these techniques, a silicon (Si) cap passivated on Ge has been the hotspot in recent years, due to its advantages of effective suppressing of interface states and good thermal stability and reliability [11]. Formation of Si passivation cap has been widely studied using chemical vapor deposition (CVD) with precursors of SiH 4 [1], Si 2 H 6 [4], Si 3 H 8 [12], and E-beam evaporation [13]. Although CVD method could provide the more uniform passivation layer over physical vapor deposition (PVD), its passivation rate has the strong correlation in channel surface orientation and the process temperature. PVD technique could provide the improved passivation rate even at room temperature, which has the advantages of low thermal budget and low cost, making it more suitable for the thin film transistors and back-endof-line 3D integration applications. In this letter, we fabricated high mobility Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces utilizing amorphous Si passivation by magnetron sputtering. Significantly improved effective hole mobility μ eff is achieved in Ge transistors compared to the Si universal mobility. Impacts of surface orientation and thickness of amorphous Si t Si on the boosting effect of amorphous Si passivation on μ eff are studied. Figure 1a shows the key process steps for fabricating Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces. After pre-gate cleaning in diluted HF (1:50) solution, ultrathin amorphous Si passivation layer was deposited on n-Ge substrates by magnetron sputtering at a target power of 50 W. Three passivation durations of 60 s, 80 s, and 100 s were used corresponding to the deposition of 0.5, 0.7, and 0.9 nm t si , respectively. After that, a 5-nm thick HfO 2 gate dielectric was deposited at 250°C by atomic layer deposition using TDMAHf and H 2 O as precursors of Hf and O, respectively. A 50-nm TaN gate electrode was deposited by reactive sputtering. Next, the gate electrode was patterned and etched, which was followed by BF 2 + implantation into source/ drain (S/D) regions at 30 KeV with a dose of 1 × 10 15 cm − 2 . Non-self-aligned S/D metals of 15-nm nickel were formed by lift-off process. Finally, rapid thermal annealing at 400°C was carried out for dopant activation and S/D metallization. Figure 1b shows the cross-sectional schematic of the Ge pMOSFET with Si/ SiO 2 interfacial layer (IL). Figure 1c shows top-view microscope image of a fabricated Ge pMOSFET. Figure 2a, b shows the transmission electron microscope (TEM) images of the high-κ/metal gate stack with SiO 2 /Si interfacial layer (IL) on Ge(001) channel with t Si of 0.5 and 0.9 nm, respectively. Insets show the highresolution TEM (HRTEM) images of the samples. For the device with a t Si of 0.5 nm, amorphous Si layer was completely oxidized, while for the device with 0.9 nm t Si , about two Si monolayers remained after the subsequent annealing steps.  Fig. 3b. Here, threshold voltage V TH is defined as the V GS at I DS of 10 −7 A/μm. It is observed that Ge(001) pMOSFET achieves the higher drive current I ON compared to the transistors on (011) and (111) surfaces at the fixed V GS -V TH . Later, we will show that this is attributed to the fact that Ge(001) pMOSFETs have a higher effective hole mobility μ eff in comparison with the devices on the other two surface orientations. We perform a comprehensive comparison of electrical performance for the devices with the fixed t Si of 0.9 nm, including I ON , leakage floor I leak , subthreshold swing (SS), and V TH characteristics. I leak is defined as the minimum I DS at V DS of − 0.05 V. Figure 4a presents the statistical plot of the I ON for Ge pMOSFETs on various orientations, and I ON was defined as I DS at a V DS of − 0.5 V and a V GS -V TH of − 0.8 V. All the transistors in this plot have the L G of 3 μm and W of 100 μm. (001)-oriented devices exhibit the improved mean I ON as compared to those on (011) and (111) orientations, which is attributed to the higher μ eff . Figure  (111)-oriented devices. It should be noted that the I leak is determined by the reverse current of the p + /n junction in drain region, which is affected by the background n-type doping concentration in Ge substrate and activation of the implanted p + dopants. The n-type doping concentrations in the wafers with various orientations are not exactly the same. The surface orientation affects the dopant activation rate and recrystallization quality of S/D regions. Furthermore, although the I G is lower than I DS before the turn-on of the transistors, it would influence the I leak . Similarly, (001)-oriented Ge pMOSFETs demonstrate the improved SS characteristics in comparison with other two orientations, which is due to that transistors on (001) surface have the lower midgap density of interface state D it compared to the other devices. Figure 4d shows that the devices on different orientations have the different V TH . Based on the results in Fig. 4, it is concluded that, with the fixed t Si of 0.9 nm, (001)-oriented Ge pMOSFETs obtain the best electrical characteristics.

Results and discussion
The thicknesses of Si/SiO 2 IL in transistors with 0.9 nm t Si on different surface orientations are studied by using inversion capacitance C inv versus V GS measurement, as shown in Fig. 5. Forward and reverse sweeping measurements exhibit the negligibly small hysteresis in the devices. The transistors exhibit the similar magnitude of C inv , 1 .56 μF/cm 2 , corresponding to the capacitive effective thickness (CET) of 2.2 nm. Figure 5b show the statistical results of saturated C inv for the devices, which demonstrate the very small difference in C inv in the transistors on different surface orientations. This indicates that the passivation rate of amorphous Si by magnetron sputtering is independent of the surface orientation. The rule of left-right shifts of the C inv -V GS curves is well consistent with that of V TH for the devices in Fig. 4d, which might be induced by the slightly different doping concentration in different orientation substrates. Figure 6 compares the mobility characteristics of the transistors with 0.9 nm t Si on various surface orientations. The μ eff was extracted using a total resistance slope-based method [14]. Ge(001) pMOSFETs exhibit the much higher channel mobility compared to the devices on (011) and (111) orientations. Transistors on (001) substrate achieve a peak μ eff of 278 cm 2 /V·s at an inversion charge density Q inv of~3.5 × 10 12 cm −2 , which is 2.97 times higher than the Si universal mobility. Surface roughness at the Si/Ge interface and density of interface states (D it ) can affect μ eff of the devices at high inversion carrier density. It is unlikely that the commercially purchased Ge wafers with various surface orientations have the obvious difference in surface roughness. Therefore, it is speculated that the mobility enhancement in (001)-oriented devices is mainly due to reduced carrier scattering contributed by interface states. In this work, we evaluate the midgap D it of the devices, and with the fixed t Si of 0.9 nm, the (001)-oriented Ge pMOSFETs indeed have the lower midgap D it compared to the other orientations.
The impact of t Si on the electrical performance of Ge pMOSFETs is also investigated. Figure 7a Fig. 8a, we see that transistors with 0.5 nm t Si achieve the improved I ON in comparison with the devices with thicker t Si , which is due to the transistor with 0.5 nm t Si that has a smaller CET, leading to a higher C inv . It is noticed that I leak decreases with the increasing of t Si (Fig. 8b), and transistors with 0.5 nm t Si has the inferior SS characteristics to those of the devices with 0.7 and 0.9 nm amorphous Si passivation layer (Fig. 8c). This might be due to those transistors with 0.5 nm t Si having a higher midgap D it . The relation between SS and midgap D it of Ge pMOS-FET can be expressed by SS = ln(10) ⋅ (kT/q) ⋅ [1 + (C it + C d )/C ox ], where C ox , C d , and C it are oxide capacitance, depletion-layer capacitance, and capacitance from interface traps, respectively. C it can be calculated by q × D it , were D it is the interface trap density. Although transistor Fig. 6 Plot of μ eff versus Q inv for Ge pMOSFETs with 0.9 nm t Si on (001)-, (011)-, and (111)-oriented substrates. Ge(001) pMOSFETs achieve the 2.97 times enhancement in μ eff at a Q inv of 3.5 × 10 12 cm −2 as compared to the Si universal mobility. The μ eff was extracted using a total resistance slope-based method [17] a b with 0.5 nm t Si has the larger C ox compared to the other two devices, its higher midgap D it can lead to the inferior SS to the devices with the thicker t Si . The surface passivation will also affect the I leak from drain to source. With the sweeping of V GS from position to negative, the channel transfers from accumulation mode to inversion mode. However, if the D it is high, some points in channel surface are pinned by the interface traps, and the leakage paths can be formed, increasing I leak from drain to source. As shown in Fig. 8d, Ge(111) pMOSFETs show the shift of V TH to negative V GS direction with the increasing of t Si , which is attributed to the increased CET. In addition, the density of traps in the lower bandgap half seems to increase for the thinner t Si , which might lead to the shift of V TH [2]. Figure 9a shows the C inv as a function of V GS curves for the Ge pMOSFETs on (111)-oriented surface with t Si of 0.5, 0.7, and 0.9 nm measured at a frequency of 300 kHz. The CET values in inversion regions are extracted to be 1.8, 1.9, and 2.2 nm for the devices with 0.5, 0.7, and 0.9 nm t si , respectively. μ eff as a function of Q inv characteristics of the devices are extracted and shown in Fig. 9b. The (111)-oriented Ge pMOSFET with 0.7 nm t si achieves the highest peak mobility of 229 cm 2 /V s, which is 2.27 times higher compared to the Si universal mobility. It should be noted that the devices with 0.5 nm t Si exhibit a significantly improved μ eff over the transistors with thicker t Si at high Q inv (e.g. 10 13 cm −2 ). This also leads to the higher I ON at high V GS -V TH in the devices with 0.5 nm t Si compared to the devices with 0.7 and 0.9 nm t Si . The μ eff at high Q inv decreases as t Si increases from 0.5 nm to 0.7~0.9 nm, which is attributed to the fact that the larger surface roughness leads to the stronger surface roughness scattering of the carriers. During the passivation of Ge surface using magnetron sputtering at room temperature, the diffusion of surface atoms is greatly suppressed. So with the increasing of t Si , the surface roughness is larger, which can be observed from the HRTEM images in Fig. 2. a b c d Fig. 8 Comparison of a I ON , b I leak , c SS, and d V TH for (111)-oriented Ge pMOSFETs with 0.5, 0.7, and 0.9 nm t Si showing that transistors with 0.5 nm t Si have the better I ON , but worse SS and I leak characteristics in comparison with devices with thicker t Si In Fig. 10, we benchmark the μ eff of the Ge pMOS-FETs in this work with those of the reported relaxed Ge transistors with Si by E-beam evaporation, SiH 4 , Si 2 H 6, and Si 3 H 8 passivation. Compared to the amorphous Si by E-beam evaporation in Ref. [15], Ge pMOSFETs in this work exhibit the significantly improved μ eff . It is seen that, at the similar CET, Ge pMOSFETs utilizing amorphous Si passivation by magnetron sputtering have the lower μ eff in comparison with the devices with Si 2 H 6 passivation. The process of passivation using amorphous Si needs to be further optimized to enhance the carrier mobility.
Ge pMOSFETs with the different t Si on (001)-oriented surface are also characterized. Figure 11a, b illustrate the measured I DS -V GS and I DS -V DS curves, respectively, of a pair of Ge(001) pMOSFETs with 0.5 and 0.9 nm t Si . Similar to the (111)-oriented devices, Ge(001) pMOSFET with 0.5 nm t Si obtains the improvement in I ON but the degradation in I leak compared to the transistor with 0.9 nm t Si .
The midgap D it characteristics of Ge pMOSFETs are studied by the method in [16], and values of D it are calculated by D it = [SSlog(e)/(kT/q) − 1]C G /q, [16] where q is the electron charge, k is Boltzmann's constant, T is the absolute temperature, and C G is the measured gate capacitance per unit area. Figure 12 shows D it as a function of the thickness of amorphous Si with various Ge surface orientations. For (111)-oriented surface, a device with 0.7-nm t si has the lowest D it value. With the 0.9 nm t Si , (001)-oriented device has the lower D it compared to the transistors on other orientations. a b Fig. 9 a C inv -V G characteristics measured at 300 kHz for (111)-oriented devices with 0.5, 0.7, and 0.9 nm t Si . b μ eff as a function of Q inv for Ge pMOSFETs [17] a b c Fig. 10 a μ eff for the Ge pMOSFETs in this work vs. the published results for relaxed Ge pMOSFETs. b, c Benchmarking of μ eff extracted at Q inv = 5 × 10 12 and 1 × 10 13 cm −2 , respectively, of the Ge pMOSFETs with the different CET values [18,19] Finally, we compare the key electrical characteristics of Ge pMOSFETs on the different orientations in Table 1. With a fixed t Si , Ge(001) pMOSFET has the improved electrical performance compared to the other two orientations. The drive current can be enhanced by reducing the t Si from 0.9 nm to 0.5 nm, which is due to that the thinner t Si provides a significantly reduced CET without causing degradation in μ eff .

Conclusions
Ge pMOSFET passivated by amorphous Si are demonstrated on (001)-, (011)-, and (111)-oriented substrate. With a t Si of 0.9 nm, the improved I ON and SS characteristics are obtained in (001)-oriented Ge pMOSFETs in comparison with the devices on (011) and (111) orientations, due to the higher μ eff and lower midgap D it . Ge(001) pMOSFETs with 0.9 nm t Si achieve a peak a b Fig. 11 a Measured I DS -V GS and I G -V GS curves of (001)-oriented Ge pMOSFETs with 0.5 and 0.9 nm t Si . b I DS -V GS curves of the devices mobility of 278 cm 2 /V s at a Q inv of 3.5 × 10 12 cm −2 , which is 2.97 times higher than the Si universal mobility. It is demonstrated that I ON of the devices is improved with the decreasing of t Si due to the reduction of CET. But Ge pMOSFETs with thicker t Si exhibit the superior subthreshold swing and leakage floor, owing to that midgap D it can be reduced by increasing t Si .