Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.


Background
With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (R on,sp ) and maximizing off-state breakdown voltage (BV) [1][2][3][4][5][6][7][8][9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of R on,sp vs. BV for LDMOS devices [10][11][12][13][14][15][16][17][18][19][20]. In our previous work, the LDMOS with ultrashallow trench isolation (USTI) was proposed [21]. The depth and corner angel of USTI were optimized to achieve best-in-class performance. However, for the low voltage LDMOS, the drift region is losing domination in R on,sp and the contribution of the channel region cannot be ignored.

Method
In this work, a novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is investigated. The physical models IMPACT.I, BGN, CONMOB, FLDMOB, SRH, and SRFMOB are used in numerical simulation. On-resistance analytical model is proposed to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. Based on the model, N-buried layer and partial P-buried layer are optimized to achieve low R on,sp and high BV. Figure 1a shows the schematic cross-section of ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer. The LDMOS features the dual-gate with N-buried layer and the partial P-buried layer which contributes to reduce R on,sp and enhance BV, respectively. In the channel region, the enhanced dual-gate is formed by trench gate and highly doped N-buried layer. Compare to conventional dual-gate structure, N-buried layer significantly reduce the resistance of the channel region by provide a low on-resistance conduction path under P-well in the on-state. In the drift region, the partial P-buried layer with high doping concentration is introduced under the N-drift region to enhance BV while maintaining low R on,sp . The partial P-buried layer helps to reduce the vertical electric field in the off-state without breaking charge balance in the drift region. The key size of the novel device is listed in Table 1. Figure 1b shows the schematic equivalent on-resistance model for the proposed LDMOS. The total on-resistance is considered as the resistance of the drift region (R d ) and the resistance of the channel region (R c ) in series. In the channel region, surface channel conduction path parallels the trench channel conduction path. Thus, R c is equal to (R chs + R acc )//(R cht + R nb ), where R chs , R acc , R cht , and R nb are the resistances of the surface-gate channel, the accumulation region, the trench gate channel, and the N-buried layer, respectively. Based on the proposed on-resistance model, the reduction of R c would achieve by decreasing R nb without affecting the other performances, because the other resistances are mainly determinate by Table 1 The key size of the novel device Fig. 1 a Schematic cross-section view of ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer. b Schematic equivalent on-resistance for the proposed LDMOS the process technology, operation voltage, and threshold voltage. The R d has been reduced by introducing P-buried layer under N-drift region to enhance the Reduce Surface-field (RESURF) effect in our previous work. In this work, the partial P-buried layer is adopted to improve the BV while maintaining the low R d .

Results and Discussion
Aiming at the reduction of R c , the N-buried layer with high doping concentration is introduced under P-well. Figure 2 shows numerical and analytical R c as functions of the doping concentration of the N-buried layer (N nb ) with single-gate and dual-gate. It is indicated that the dual-gate structure helps to reduce R c compared with the single-gate. When N nb = N d = 5.5 × 10 16 cm −3 , R c is 110 mΩ. According to the on-resistance model, R nb is the main contributor to R c . And then, the R nb is desired to decrease with the aim of smaller R c . As shown in Fig. 2a, R c is reduced with N nb increasing. When N nb = 1.35 × 10 17 cm −3 , R c is reduced to 85 mΩ. However, Fig. 2 also shows that N nb would be limited by punch-through breakdown. Because of adding trench gate, R c is decreased firstly by 34% with N nb = N d = 5.5 × 10 16 cm −3 . As N nb increases, R c continuously decreases. With optimized N nb = 1.05 × 10 17 cm −3 , R c is decreased by 45% at last. When N nb > 1.05 × 10 17 cm −3 , punch-through breakdown will happen in P-well. The analytical result of R on,sp shown in Fig. 2 indicates that the proposed model provides a good fitting with numerical simulation results. Therefore, the model is believable to guide the optimization design. Figure 3a shows numerical BV as a function of N nb with different doping concentration of P-well (N pwell ). N nb has an effect on not only the R c , but also the BV. For a given N pwell , BV keeps unchanged at small N nb , and then decreases with N nb increasing. When N nb increases to 1.2 × 10 17 cm −3 , BV starts to drop with N pwell = 2 × 10 17 cm −3 . The drop of BV is ascribed to punch -through breakdown in the P-well region as shown in Fig. 3b. As drain voltage increases, the depletion region in P-well extends to the source. When the depletion region attacks the N+/P-well junction, the punch-through breakdown occurs. For a large N pwell , the depletion mainly extends to the drift region, and the punch-through In order to achieve low R d and high BV, partial P-buried layer is introduced under the N-drift region. Figure 4a shows BV as a function of ΔL pb with different N pb . For a given N pb , as ΔL pb increases, BV increases and then decreases slightly. When ΔL pb = 0.1 μm, N pb = 1 × 10 17 cm −3 , BV reaches the maximum value 43 V. The insert shows the equipotential contour profile with N pb = 1 × 10 17 cm −3 . It is indicated that the equipotential contour in the partial P-buried layer structure extends more to substrate with comparison to full P-buried layer. Fig. 4 a BV as a function of ΔL pb with different N pb . The insert is the equipotential contour profile with N pb = 1 × 10 17 cm −3 . b Electric field distribution at the surface and the P-buried/N-drift junction interface Figure 4b shows electric field distribution at the surface and the P-buried/N-drift junction interface. For optimized conventional LDMOS, the breakdown occurs usually at the N-drift/P-buried interface. For the proposed LDMOS, the junction of N-drift/P-sub replaces the junction of N-drift/P-buried to relax the vertical electric field and extend depletion region, which results in a higher BV while maintaining low R d .

(a) (b)
Charge balance between N-drift and partial P-buried layer is required to achieve high BV. Figure 5a shows that numerical and analytical BV and R on,sp as functions of the doping concentration of the P-buried (N pb ) for different N d . For a given N d , BV has a maximum value with varied N pb , and the maximum of BV increases with the decrease of N d . However, R on,sp can be increased as the N d decreasing. Due to BV required higher than 40 V,  Figure 5b shows numerical and analytical BV and R on,sp as functions of the thickness of the STI layer (T sti ). T sti has strong impact on BV and R on,sp , and it should be designed and optimized carefully as well as our previous work [21]. For T sti < 0.3 μm, the breakdown point under the edge of poly field plate has a high electric field peak. As T sti increases, the electric field peak is relaxed, and then BV increases. For T sti = 0.3 μm, BV of 43 V is obtained. For T sti ≥ 0.3 μm, the electric field peak under the edge of poly field plate is enough low, as a result, the breakdown point transfers to P/N junction under the drain side. As T sti increases, BV increases and then saturates. Figure 6 shows the benchmark of existing Bipolar-CMOS-DMOS (BCD) technologies and the proposed LDMOS. Apparently, the process technology for proposed LDMOS is compatible with our developed BCD technology which achieved the best-in-class performance of LDMOS. In the fabrication process for the proposed LDMOS, N-buried layer could share the same mask with P-well. For the proposed LDMOS, R on,sp is 8.5 mΩ·mm 2 while BV = 43 V, which is reduced by about 37% compared with our previous work.

Conclusion
A novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is proposed and investigated by numerical simulation in this paper. N-buried layer with high doping concentration is utilized to achieve enhanced dual-gate with reducing R c . Partial P-buried layer is introduced under the N-drift region to enhance BV with keeping charge balance. The fabrication process of the LDMOS in this work is compatible with the existing BCD technology reported in our previous work. The result shows that the R on,sp of the proposed LDMOS is reduced by 37% at BV of 43 V compared with previous work. With the semiconductor processing technology going to nanometer level, the R on,sp can reduce further with channel length decrease.