Comparative Study of Negative Capacitance Field-Effect Transistors with Different MOS Capacitances

We demonstrate the negative capacitance (NC) effect of HfZrOx-based field-effect transistors (FETs) in the experiments. Improved IDS, SS, and Gm of NCFET have been achieved in comparison with control metal oxide semiconductor (MOS) FET. In this experiment, the bottom MIS transistors with different passivation time are equivalent to the NC devices with different MOS capacitances. Meanwhile, the electrical properties of NCFET with 40 min passivation are superior to that of NCFET with 60 min passivation owing to the good matching between CFE and CMOS. Although SS of sub-60 mV/decade is not achieved, the non-hysteretic transfer characteristics beneficial to the logic applications are obtained.


Introduction
With the scaling down of transistor, the integration level of integrated circuit (IC) is continuous growing. An accompanying power dissipation problem is urgent to be solved. In order to circumvent this problem, the operation voltage of the transistor should be reduced [1]. The subthreshold swing (SS) of MOSFET cannot be below 60 mV/decade at room temperature, which restricts the reduction of threshold voltage V TH and supply voltage V DD [2]. Many efforts have been devoted to the research and the development of devices with novel transport and switching mechanisms to beat the Boltzmann limit, including negative capacitance field-effect transistor (NCEFT) [3,4], resistive gate FET [5], nanoelectro mechanical FET (NEMFET) [6,7], impact ionization metal-oxide-semiconductor (I-MOS) [8,9], and tunneling FET [10,11]. Among them, NCFET has aroused much attention because it can achieve a steep SS without losing the drive current [12][13][14][15]. Doped HfO 2 (e.g., HfZrO x (HZO) and HfSiO x ) has been widely used in NCFETs [4,16,17]; it is compatible with the CMOS process [18]. A theoretical study has shown that the undesired hysteresis occurs due to unmatched ferroelectric capacitance C FE to underlying MOS capacitance C MOS in NCFET [19]. However, the effect of matching between C FE and C MOS on the electrical characteristics of NCFETs is still a concern in the experiments.
In this work, the electrical characteristics of NC Ge FETs with different MOS capacitances are studied based on the different matching between C FE and C MOS . Although SS less than 60 mV/decade does not appear, the hysteresis-free transfer characteristics and better electrical properties are obtained. Apparent peaks of C FE versus V FE curves demonstrate NC effect of HZO based NCFETs. The better matching of C FE and C MOS contributes to steeper SS and higher on current, which is beneficial to the logic applications.

Methods
The key fabrication process of Ge NCFETs is shown in Fig. 1a. Four-inch n-Ge(001) wafers with a resistivity of 0.088-0.14 Ω·cm were used as the starting substrates. After pre-gate cleaning, Ge wafers were loaded into an ultra-high vacuum chamber for surface passivation using Si 2 H 6 . Two passivation durations of 40 and 60 min were used. Then, TaN/HZO/TaN/HfO 2 stack was deposited. The thicknesses of the HfO 2 dielectric layer and HZO   NCFETs passivated for 40 min have a better matching between C MOS and C FE over the NC devices with 60 min. Figure 4b shows that NCFETs obtain 26.4% and 51.3% improvement in maximum transconductance G m,max for 60 min and 40 min surface passivation, respectively, in comparison with the control devices. It is seen that the control MOSFETs with surface passivation for 40 min have a higher I DS and G m,max than the devices passivated for 60 min, which is due to the larger C MOS induced by the smaller equivalent oxide thickness (E OT ). The internal metal gate provides an equipotential plane; the device can be equivalently modeled as a capacitive voltage divider. The total capacitance C G is a series of C FE and C MOS . The internal gate voltage is amplified owing to the NC effect. The internal voltage amplification coefficient β = | C FE | / | C FE | − C MOS gets the maximum when |C MOS | = |C FE | [20,21]. Achieving the optimized matching of C FE and C MOS is the prerequisite of the improvement of on current. The extracted V int versus gate voltage V GS curves are shown in Fig. 5a. V int of NC transistor can be extracted on account of the hypothesis that I DS -V int curve of NC transistor is exactly identical with I DS -V GS curve of the control device. The internal voltage amplification coefficient dV int /dV GS is shown in Fig. 5b. dV int /dV GS > 1 is achieved in the wide sweeping range of V GS for the NCFET with 40 min surface passivation, contributing to a steeper SS than the control device during the measuring process, which is due to the local polarization switching [22]. It is consistent with the aforementioned results in Fig. 2b. For the NCFET with 60 min passivation, the internal voltage amplification coefficient dV int /dV GS > 1 is achieved during the range of V GS < 0 V for the double sweeping of V GS , which is in agreement with the elevated SS in Fig. 3b. Figure 6a shows the extracted C MOS versus V GS curves for NC transistor, which is relying on the V int -V GS in Fig.  5a and the C G -V GS curves of control MOSFETs. The extracted C MOS is in good agreement with the measured C G.

Results and Discussion
Hence, the validity of the calculation method is demonstrated. The C FE and C MOS versus V FE curves are depicted in Fig. 6b. From the initiation of NC effect, the absolute value of negative C FE of the transistor exceeds C MOS for double sweeping of V GS all the time in Fig. 6b. |C FE | > C MOS and C FE < 0 can cause hysteresis-free characteristics, and the matching of C MOS and C FE is beneficial to the logic applications [23,24]. Hysteresis-free characteristics in Figs stable polarization switching is responsible for the nonhysteretic characteristics [26]. Furthermore, the large internal gate gain dV int /dV G > 1 is ascribed to the slight discrepancy between |C FE | and C MOS in the subthreshold region, resulting in the steep SS of NC device. Meanwhile, there is a better matching between C FE and C MOS for the NCFET with 40 min passivation than the NCFET with 60 min passivation. Thus, this provides direct evidence to indicate that the NCFET with 40 min passivation possesses a better electrical performance than the NCFET with 60 min passivation. The FE polarization changes the V FE ; hence the charge of FE varies. The total charge multiplies, which is attributed to the FE polarization besides the increment of V GS . In other words, for the given V GS , the charge in the channel increases so the I DS improves. As a consequence, the steep SS of transfer characteristic appears in the experiments.

Conclusions
The hysteresis-free transfer characteristics are obtained for the NCFETs with 40 and 60 min passivation. NC Ge pFETs with 40 min passivation have better electrical characteristics than the NC device with 60 min passivation in experiments. We also demonstrate the NC effect of HZO based NCFETs. For NCFETs, the steep SS and dV int /dV GS > 1 are obtained. The NCFET with 40 min passivation has achieved a good matching between C FE and C MOS , which contributes to the non-hysteretic characteristics. The different NC behaviors are considered to be related to the microscopic domain wall switching in the FE thin films.