Ge N-Channel MOSFETs with ZrO2 Dielectric Achieving Improved Mobility

High-mobility Ge nMOSFETs with ZrO2 gate dielectric are demonstrated and compared against transistors with different interfacial properties of ozone (O3) treatment, O3 post-treatment and without O3 treatment. It is found that with O3 treatment, the Ge nMOSFETs with ZrO2 dielectric having a EOT of 0.83 nm obtain a peak effective electron mobility (μeff) of 682 cm2/Vs, which is higher than that of the Si universal mobility at the medium inversion charge density (Qinv). On the other hand, the O3 post-treatment with Al2O3 interfacial layer can provide dramatically enhanced-μeff, achieving about 50% μeff improvement as compared to the Si universal mobility at medium Qinv of 5 × 1012 cm−2. These results indicate the potential utilization of ZrO2 dielectric in high-performance Ge nMOSFETs.

Background GERMANIUM (Ge) has exhibited advantages of higher carrier mobility and lower processing temperature compared with Si devices. These make Ge to be an alternative for applications of ultrascaled CMOS logic devices and thin-film transistors (TFTs) as top layer in threedimensional integrated circuits [1][2][3]. In the past few years, great efforts have been focused on surface passivation, gate dielectric, and channel engineering for Ge p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), which have contributed to significant improvement in electrical performance for the p-channel devices.
But for Ge n-channel MOSFETs, low effective carrier mobility (μ eff ) caused by poor interfacial layer of gate stack strongly limits the performance of the devices. Various surface passivation techniques including Si passivation [1], plasma post-oxidation [4], and InAlP passivation [5] and several high-κ dielectrics including HfO 2 , ZrO 2 [6][7][8], Y 2 O 3 [9], and La 2 O 3 [10] have been explored in Ge nMOSFETs to boost the electron μ eff . It was demonstrated that ZrO 2 dielectric integrated with Ge channel can provide a robust interface due to that a GeO 2 interfacial layer can react and intermix with the ZrO 2 layer [7]. A decent hole μ eff has been reported in Ge p-channel transistors [6][7][8], while there is still a lot of room for improvement in electron μ eff for their counterparts.
In this work, Ge nMOSFETs with ZrO 2 gate dielectric are fabricated to achieve improved μ eff over Si in the entire range of inversion charge density (Q inv ). Ge transistors obtain a 50% improvement in electron μ eff compared to the Si universal mobility at a medium Q inv of 5.0 × 10 12 cm −2 .

Experimental
The key process steps for fabricating Ge nMOSFETs on 4-inch p-Ge(001) wafers with a resistivity of 0.136-0.182 Ω cm are shown in Fig. 1a. The source/drain (S/D) regions were implanted with phosphorous ion at a dose of 1 × 10 15 cm −2 and an energy of 30 keV followed by dopant activation annealing at 600 °C. After the pre-gate cleaning, Ge wafers were loaded into an atomic layer deposition chamber for the formation of the gate dielectric layer(s): After that, a 25-nm-thick Ni layer was deposited in S/D regions. Finally, the post-metallization annealing (PMA) at 350 °C for 30 s was carried out to form the Ni germanide and improve the interface quality. Schematic and microscope images of the fabricated transistor are shown in Fig. 1b, c, respectively. Figure 2a, b shows the high-resolution transmission electron microscope (HRTEM) images of the gate stacks on wafers A and B, respectively. The unified thickness of the Al 2 O 3 /GeO x interfacial layer (IL) for wafer A is ~ 1.2 nm indicating the 0.2-0.3 nm GeO x . For the device on wafer B, an ultrathin GeO x IL was experimentally demonstrated [7].

Results and Discussion
The measured capacitance (C) and the leakage current (J) characteristics for Ge MOS capacitors on wafers A, B, and C are measured and shown in Fig. 3a, b, respectively. The equivalent oxide thickness (EOT) of the devices on wafers A, B, and C is extracted to be 1.79, 0.59, and 0.83 nm, respectively. Assuming the GeO x IL provides an extra EOT of ~ 0.25 nm for wafers A and C by comparing wafers B and C, the 3.3 nm ZrO 2 contributes an EOT of ~ 0.6 nm with κ value of ~ 21.8, which is consistent with the previous reported value of amorphous ZrO 2 [11]. These derived results also confirm that the thickness in GeO x IL on wafer B is negligible.
The GeO x /Al 2 O 3 IL for wafer A and GeO x IL for wafer C produces the EOT of ~ 1.2 and ~ 0.25 nm, respectively. The EOT of the devices can be further reduced by decreasing the IL thickness or improving the interface quality, and enhancing the permittivity of ZrO 2 with some surface passivation, e.g., NH 3 /H 2 plasma treatment [6]. Figure 3c compares J versus EOT characteristics for the Ge nMOSFETs in this work against values for other reported Ge devices [5,[12][13][14][15][16][17]. It is also observed that the results are consistent with the reported Ge MOS with ultra-thin EOT following the same trends, indicating the difference of leakage current shown in Fig. 3b should be mainly attributable to the difference of EOT. Figure 4a shows measured drain current (I D ) and source current (I S ) versus gate voltage (V G ) curves of Ge nMOSFETs from wafers A, B, and C. All transistors have a gate length L G of 4 μm and a gate width W of 100 μm. The point subthreshold swing (SS), defined as dV G /d(logI D ), as a function of I D curves for the transistors in Fig. 4a is calculated and shown in Fig. 4b. It is clarified that the transistor on wafer A exhibits the degraded I D leakage floor and SS compared to the devices on wafers B and C. Besides the increase in EOT in devices on wafer A would bring in the increment of SS, these phenomenon should be partly attributed to the fact that the device with the Al 2 O 3 inserted layer has a higher density of interface traps (D it ) within the bandgap of the Ge channel in comparison with the wafers B and C. Figure 4c shows the measured output characteristics, i.e., I D -V D curves for various values of gate overdrive |V G -V TH | of the devices demonstrating that the Ge transistor on wafer A achieves significantly improved drive current compared to the devices on wafers B and C. Here, V TH is defined as V GS corresponding to an I D of 10 −7 A/ μm. Considering the identical conditions for S/D formation, the boosted I DS for transistors on wafer A indicates the higher μ eff [18][19][20][21]. The Al 2 O 3 layer has not led to the degradation of D it performance near the conduction band of the Ge channel. Figure 5a shows the total resistance R tot as a function of L G for the Ge nMOSFETs with ZrO 2 dielectric with an L G ranging from 2 to 10 µm. The values of R tot are extracted at a gate overdrive of 0. 6 V and a V D of 0.05 V. The S/D resistance R SD of the transistors is extracted to be ~ 13.5 kΩ μm, utilizing the fitted lines intersecting at the y-axis. The similar R SD is consistent with the identical process of PMA and S/D formation. The channel resistance R CH values of the devices are obtained by the slope of the fitted lines, i.e., ΔR tot /ΔL G , which can be used for calculating the μ eff characteristics of Ge nMOSFETs. To evaluate the interface quality, interface trap densities (D it ) were extracted by the following equation according to Hill's method [17]: where q is the electronic charge, A is the area of the capacitor, G m,max is the maximum value of measured conductance, with its corresponding capacitance C m , ω is the angular frequency, and C ox is gate oxide capacitance. The D it values are calculated to be 3.7, 3.2, and 2.3 × 10 12 eV −1 cm −2 for the devices on wafers A, B, and C, respectively. It is known that the calculated values correspond to the midgap D it . The device with Al 2 O 3 IL on wafer A has a higher midgap D it compared to the devices on wafers B and C. This is consistent with the results in Figs. 3a and 4a, and the higher midgap D it gives rise to a larger depletion capacitance dispersion in wafer A causing a higher leakage current of I DS in comparison with the other two wafers. Note the wafer A should have the lower D it near the conduction bandgap due to its higher μ eff over wafers B and C. It is well known that μ eff is the bottleneck for high drive current and transconductance in Ge nMOSFETs. Here, μ eff can be calculated by µ eff = 1/[WQ inv (�R tot /�L G )] , where ΔR tot /ΔL G is the slope of the R tot versus L G as shown in Fig. 5a. Q inv can be obtained by integrating the measured C inv -V G curves. In Fig. 5b, we compare the μ eff versus Q inv of the Ge nMOSFETs on wafers A, B, and C with those reported previously in [18,[22][23][24][25]. The extracted peak μ eff values of the transistors on wafers A and C are 795 and 682 cm 2 /V s, respectively, and that of Ge nMOSFETs on wafer B is 433 cm 2 /V s. Ge nMOSFETs with Al 2 O 3 IL achieve a significantly improved μ eff in comparison with the transistors on wafer B or C, the devices in [18,[22][23][24][25] in a high field, and Si universal mobility in the entire Q inv range. At a Q inv of 5 × 10 12 cm −2 , a 50% μ eff enhancement is achieved in devices on wafer A as compared to the Si universal mobility. This demonstrates that by protecting the channel surface for preventing the intermixing of ZrO 2 and GeO x using Al 2 O 3 , a high-quality interface between gate insulator and Ge is realized to boost the mobility characteristics, which is also reported in the previous studies of Ge MOSFETs with ultrathin EOT [26]. μ eff in transistors on wafer C is higher than the Si universal at a Q inv of 2.5 × 10 12 cm −2 , although it rapidly decays with the increase in Q inv range. This indicates that the used O 3 oxidation before ZrO 2 deposition would improve the interfacial quality to some extent; however, it does not lead to enough flat channel surface to effectively suppress the surface roughness scattering of the carrier at high Q inv due to the intermixing of ZrO 2 and GeO x, since it is reported that the generation of oxygen vacancies during the intermixing would increase the short-range order (SRO) roughness [27]. Optimizing the O 3 oxidation process or reducing the Al 2 O 3 IL thickness can make the Ge transistor achieve a reduced EOT while maintaining a higher μ eff at the high Q inv .

Conclusions
The impacts of gate dielectric structure and morphology on Ge nMOSFET electrical characteristics are investigated. An Al 2 O 3 /ZrO 2 gate dielectric provides for significantly-improved μ eff as compared to the Si universal mobility. μ eff can be improved by inserting an Al 2 O 3 layer between the ZrO 2 and Ge channel, which, however, inevitably leads to a larger EOT. Al 2 O 3 -free Ge nMOS-FETs with O 3 oxidation of the Ge surface prior to ZrO 2 deposition achieve a peak μ eff of 682 cm 2 /V s which is higher than that of Si at the similar Q inv .