Synaptic Behaviors in Ferroelectric-Like Field-Effect Transistors with Ultrathin Amorphous HfO2 Film

We demonstrate a non-volatile field-effect transistor (NVFET) with a 3-nm amorphous HfO2 dielectric that can simulate the synaptic functions under the difference and repetition of gate voltage (VG) pulses. Under 100 ns write/erase (W/E) pulse, a memory window greater than 0.56 V and cycling endurance above 106 are obtained. The storied information as short-term plasticity (STP) in the device has a spiking post-synaptic drain current (ID) that is a response to the VG input pulse and spontaneous decay of ID. A refractory period after the stimuli is observed, during which the ID hardly varies with the VG well-emulating the bio-synapse behavior. Short-term memory to long-term memory transition, paired-pulse facilitation, and post-tetanic potentiation are realized by adjusting the VG pulse waveform and number. The experimental results indicate that the amorphous HfO2 NVFET is a potential candidate for artificial bio-synapse applications.


Background
The need for high density, high performance, and low power consumption has necessitated the development of novel memory devices. Because of their compact structure, non-destructive read-out operation, and multi-bit storage, non-volatile transistors such as ferroelectric field-effect transistors (FeFETs), floating-gate transistors, and IGZO memristors have attracted much attention for embedded memories, computing-in memory, and neuromorphic synapse applications [1][2][3][4][5]. The stimulus is applied to the gate electrode of the transistors for synaptic operation, and the drain side current is the post-synapse current [6,7].
Recently, non-volatile field-effect transistors (NVFETs) utilizing amorphous Al 2 O 3 and ZrO 2 gate insulators were experimentally realized, which was attributed to the switchable polarization (P) induced by the voltagemodulation of the oxygen vacancy ( V + O )-related dipoles [8][9][10][11]. The mechanism of voltage-modulation of V + O in ferroelectric tunnel junctions was also demonstrated, which improved the tunneling electroresistance ratio of the device [12]. Compared to the polycrystalline doped-HfO 2 FeFETs, NVFETs with amorphous dielectrics exhibited significantly lower operation voltage and better linearity for multi-threshold voltage operation [9]. These characteristics make them a promising candidate for lowpower neuromorphic devices that closely mimic biological behaviors, which are not to be investigated yet.
In this work, biological synapse behaviors such as short-term plasticity (STP), long-term potentiation (LTP), the transition from short-term memory (STM) to long-term memory (LTM), and spike-timing-dependent plasticity (STDP) are emulated based on the single amorphous HfO 2 NVFET, without using additional circuit elements.

Methods
The process flow in [9] was used to fabricate the NVFETs with an amorphous HfO 2 gate insulator on 4-inch n-type Ge(001). After the pre-gate cleaning, the substrate was loaded into an atomic layer deposition (ALD) chamber to deposit the HfO 2 at 300 °C. Then, a 100-nm-thick TaN gate electrode was deposited by the reactive sputtering. After the gate electrode patterning and etching, the source/drain (S/D) regions were implanted by BF 2 + . 20-nm thick nickel (Ni) S/D metal electrodes were formed by a lift-off process. Finally, the repaid thermal annealing (RTA) at 350 °C was carried out to improve the interface quality and form the Ni germanium silicide S/D contacts.
The schematic of the fabricated NVFET is shown in Fig. 1a. Figure 1b shows a 3-nm-thick amorphous HfO 2 imaged with high-resolution transmission electron microscopy (HRTEM). Figure 1c depicts the measured ferroelectric-like P vs. voltage (V) behavior in the amorphous HfO 2 capacitor at a frequency of 1 kHz. The underlying mechanism for the ferroelectric-like behaviors in this amorphous HfO 2 devices is similar to that for those devices in Refs. [8,9]. The extracted evolution of the remnant P (P r ) and coercive voltage (V c ) for the device during the endurance test is shown in Fig. 1d. No wake-up or imprint is observed over 10 6 cycles. A positive-up and negative-down (PUND) test is used to extract the switching current component of the device by isolating the non-switching charge (Fig. 1e), demonstrating the true P.

Results and Discussion
In contrast to the trapping/detrapping process [13][14][15], a ferroelectric-like clockwise hysteresis loop is observed for the DC sweeping of the drain current (I D ) as a function of gate voltage (V G ) curves for the transistor with the amorphous HfO 2 gate insulator, as shown in Fig. 2a. The non-volatile memory function is induced by the ferroelectric-like P switching in the gate stack. Figure 2b shows the initial I D -V G curve for the device and those underwent with 100 ns, 1 μs, 10 μs, 100 μs, and 1 ms write/ erase (W/E) pules at ± 3 V voltage providing a non-volatile memory function, respectively. The device has a gate length (L G ) of 3 μm and a gate width (W) of 80 μm. The write (erase) operation is achieved by applying positive (negative) voltage pulses to the gate of the HfO 2 FET, to raise (lower) its threshold voltage (V TH ). Figure 2c plots the MW values for different W/E pulse widths. As the pulse width increases from 100 ns to 10 μs, the MW increases to 1.2 V; but when the W/E pulse width further increases, the MW decreases. Trapping/detrapping process is thought to cause the degradation of MW under the 100 μs to 1 ms W/E pulses. Here, MW is the V TH difference between the two states, and V TH is defined as V G at I D = 100 nA⋅W/L G .
As shown in Fig. 2d, a stable MW is maintained over 10 6 W/E cycles. Figure 2e shows that a stable MW of the amorphous HfO 2 device can be maintained over several hundred seconds. The limitation retention time of the device is mainly due to the smaller P r and large depolarization field. Recent studies have shown that the non-volatile devices with limited retention time can be alternative candidates for high-density and lower power DRAM architectures [16,17].
Synapse is a basic unit of the human neural network to realize the information transmission from the pre-synaptic neuron to the post-synaptic neuron. The STP is a key factor that affects the biographic performance of the NVFET synapse in the neural system [18]. Figure 3 shows the STP characteristics of a HfO 2 NVFET under the single V G pulse with a fixed pulse magnitude of -3 V. The V G pulse width varies from 1 μs to 10 ms and the base voltage varies from 0.5 V to − 1.5 V. As a three-terminal device, the STP performance can be modulated by changing the base voltage, magnitude, and width of the V G pulses. Underwent an applied V G stimulus, the postsynaptic I D of the device increases to a high I D state and decays to a low I D state when the V G pulse ended. For all the measurements, the devices are in the same relaxed pre-state. As shown in Fig. 3a, underwent a 1 μs V G pulse, the device exhibits a lower post-synaptic I D under the base voltage of − 1.5 V and − 1.0 V compared to the cases under 0 V and − 0.5 V V G base. It is speculated that this could be due to the smaller difference between base and pulse V G voltages. As the V G pulse is widened to ms, the post-synaptic I D no longer depends on the base voltage (Fig. 3c, d). In general, the post-synaptic I D of the device is improved with widening the stimulus V G pulse.
According to Fig. 3, there is a refractory period after the V G pulse. The I D barely varies with the V G , which accurately simulates the bio-synapse with the external stimulating signal. The refractory period of the NVFET synapse is approximately 10-100 μs, which does not depend on the V G pulse width or magnitude. Figure 4 depicts the post-synaptic I D of the transistor that underwent multiple V G input pulses within the refractory period. During this period, I D is excitable by the V G pulse, but its value is less than that for the initial pulse firing. After the refractory period, the post-synaptic I D increases with time to a saturate state, and values of post-synaptic I D in saturation increase with the decrease in the base voltage.
Besides the width and magnitude of the pulse, the stimulation rate also influences the memory formation of the device. To examine the effects of the stimulation rate on the transistor, the ten cycles (N = 10) of stimuli/read V G are applied to the gate electrode. As shown in Fig. 5a, during the stimuli or read, the amplitude and time of the V G pulse are fixed, and the cycle period T is changed by varying the interval parameter. The I D of the transistor was read at low voltage immediately after each stimulation pulse, which is denoted by I 1 , I 2 , …, I 10 [19].
The dynamic change in the I D of the amorphous HfO 2 NVFET under a series of V G pulses with the different T at a V DS of − 0.5 V is shown in Fig. 5b. The I D (i.e., ΔI D /I 1 ) of the device increases with the stimuli T numbers to mimic the memory behavior in the biological system. Here, ΔI D is calculated by I N − I 1 , (N = 1, 2, …, 10). Note that the I D of the device increases, i.e., (ΔI D /I 1 ) with the reduced T. With a high stimulation rate being the most effective and Fig. 2 a Dual-direction sweeping of I D -V G curves of the amorphous HfO 2 NVFET. b Measured I D -V G curves of the device with ± 3 V W/E pulses, and the pulse width varies from 100 ns to 1 ms. c MW for the amorphous HfO 2 NVFET with various pulse width. d Stable MW maintains after 10 6 W/E cycles underwent ± 3 V, 100 ns W/E pulses. e Several hundred seconds retention time was maintained of the amorphous HfO 2 device a low stimulation rate being the least effective for transforming from STM to LTM. Figure 5c plots the (I 2 − I 1 )/I 1 and (I 10 − I 1 )/I 1 , which represent the experimental conditions for paired-pulse facilitation (PPF) and post-tetanic potentiation (PTP) used in biological studies, respectively [20,21]. The PPF and PTP phenomena in our amorphous HfO 2 synaptic transistor can be compared to synapses in biology. If be former, the synaptic response is enhanced when one stimulus is followed by the same stimulus soon after; if be latter, the synaptic transmission gradually increases with the number of stimuli when a series of stimuli are received [20][21][22]. These verify the feasibility of the amorphous HfO 2 device in realizing the transformation of simulated biological memory. The error bars reflect the standard deviation when repeating the measurement a few times to prove the correctness of the data and minimize fluctuations in data.
The temporal relationship of activity between the preand post-synaptic neurons is another important aspect of the synapse. We define t PRE and t POST as the arrival times of the pre-spike and the post-spike, respectively. The change in synaptic weight (Δw) is a function of the Δt (Δt = t PRE − t POST ) between pre-and post-synaptic activity [23]. For a given stimulation, LTD will occur if Δt > 0, while LTP will occur if Δt < 0. STDP is defined as the change in synaptic weight of the Δt between preand post-synaptic activity. By utilizing the waveforms adopted in Fig. 6a, b, the STDP curves for the amorphous HfO 2 NVFET-based synapse are extracted with 100 ns spikes and shown in Fig. 6c. The pre-and the post-spike resembling the output of the leaky integrateand-fire neurons are constitutive of an initial negative pulse followed by a sequence of positive pulses with the decreased amplitude. As shown in Fig. 6c, the amorphous HfO 2 NVFET can stimulate the STDP learning

Conclusions
In this work, we report an ultrathin amorphous HfO 2 NVFET to emulate the bio-synapse. An MW of 0.56 V with an endurance above 10 6 cycles is experimentally demonstrated under the ± 3 V and 100 ns W/E pulses. Furthermore, various synaptic behaviors including STP under different stimuli, transitioning from STM to LTM, PPF, PTP, and STDP performance are realized in the device.