Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (VGC,ST) and anode–cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of − 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.


Introduction
The scaling down of dynamic random-access memory (DRAM) cell has been continuously required for highdensity, high-speed, and low-power operations [1][2][3] However, the conventional one transistor-one capacitor (1T-1C) DRAM is facing an inevitable problem: it is increasingly difficult to achieve the required capacitance to differentiate the two states (~ 10 fF/cell) with the smaller cell area [4]. Even though there have been many studies to improve the capacitor technologies, such as new high-k materials [5][6][7] and a high-aspect-ratio 3D capacitor structure [8,9], these approaches possess the issue of increasing fabrication complexities and high cost [2,3]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based randomaccess memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10][11][12][13][14][15][16]. The TRAM can operate as a two-terminal (2-T) device by modulating the energy band with only the anode and cathode biases [10][11][12]. 2-T TRAM has the advantage of its simple structure that allows a cost-effective cross-point array fabrication with conventional Si processes. Yet, the drawbacks are the low data retention and array disturbance that stem from the weak controllability and asymmetric of the storage areas [10][11][12]. The 2-T TRAM has a limit to overcome these drawbacks by controlling the two storage areas with only anode-cathode bias because electrons and holes exhibit a difference in mobility and lifetime. On the other hand, a three-terminal (3-T) TRAM, whose gate bias controls the energy band of the storage region, can remedy these drawbacks; the proper adjustment of gate-cathode voltage (V GC ) can improve the retention characteristics and the array disturbance immunity by anode-cathode voltage (V AC ) [13][14][15][16]. But an array operating conditions using the standby voltages for continuous retention characteristics and high disturbance immunity have not been reported yet. In terms of cell density, if a vertical channel transistor (VCT) is adopted, 4F 2 memory feature size can be achievable with the 3-T TRAM [17,18].
This paper aims at providing memory operating voltage guidelines with optimized standby voltages in the 3-T TRAM array configurations. The effects of the gate-cathode voltage on the standby state (V GC,ST ) are thoroughly investigated for low-power operations and better retention characteristics. To maintain the stored charges in the storage area with the lowest standby current, a minimum anode-cathode voltage on the standby state (V AC,ST ) is obtained from the anode current-anode voltage characteristics (I A -V AC ). Furthermore, for a reliable array operation, the operating conditions are suggested to avoid any possible array disturbance using the optimal standby voltage. Figure 1 shows a schematic diagram of a 3-T TRAM unit cell and a possible cross-point vertical array configuration. The 3-T TRAM consists of physical p + -anode-nbase-p-base-n + -cathode layers with a gated p-base. The anode and cathode areas are highly doped with a doping concentration of 1 × 10 20 cm −3 , and the base areas (p-and n-base) have the same Gaussian doping profile with a peak value of 1.6 × 10 18 cm −3 , which have similar doping concentrations in real device. This symmetric doping profile can secure memory hysteresis characteristics and sufficient memory window margin. If the lengths of both n-and p-bases are shorter than the sum of the depletion width inside the storage areas, sensing margin and storage capacity are reduced. On the other hand, when the length of both bases is longer than the sum of the depletion width, the robustness of the memory structure is worsened due to the high vertical aspect ratio of the 3-T TRAM. Therefore, the lengths of both nand p-bases are set to 100 nm considering the junctions' depletion widths [12]. The channel area is 20 × 20 nm 2 , and the thickness of the gate oxide is 5 nm. The gate and cathode electrodes are designed as a word line (WL) and a bit line (BL), respectively.

Simulation Methods
Si-based 3-T TRAM cells are simulated using Sentaurus technology computer-aided design (TCAD) [19]. To reliably simulate the Si-based 3-T TRAM, the physics models of the simulation are adjusted by using the experimental data of I A − V AC characteristics for various V GC s in the Si-based thyristor memory device with a gated base ( Fig. 2) [20]. Specifically, the parameters of the recombination model are adjusted and the Si-SiO 2 surface SRH recombination model is adopted to reflect the data retention characteristics of real devices affected by junction and interface defects. Usual drift-diffusion transport model with Fermi-Dirac distribution is used. Philips unified mobility model is adopted to consider the carrier-impurity and carrier-carrier scatterings [21], and the high-field saturation and doping-dependent mobility models are also used. Oldslotboom bandgap narrowing model [22] is used to consider the highly doped silicon regions. Doping-dependent Shockley-Read-Hall (SRH) [23] and Auger recombination [24] models are adopted to account for the carrier recombination at the junctions. The avalanche generation [25] and band-to-band tunneling [26] models are also considered to calculate the carrier generations and the tunneling. The pulses applied to all memory operations have the rise time (T rise ) and the fall time (T fall ) of 0.25 ns, while the hold time (T hold ) is  adjusted to the experimental data (symbols) of the p + −n−p−n + silicon memory device with a gated base 2 ns [12]. The operation speed inferred from these pulse parameters is comparable to the modern DRAM memory clock rate [27].  Figure 3b shows the stored hole density in the p-base (N P ) as a function of standby time at state-1 (T ST,1 ) after the program pulse. As the T ST,1 increases, the N P decreases due to the carrier recombinations at the junctions. Due to the low V AC,P , the device with V GC,ST of − 0.4 V exhibits lower N P than the case of 0.0 V in the early stage (T ST,1 < 10 μs). However, the N P in the later stage (T ST,1 > 10 s) is higher than the case of 0.0 V. This higher N P is the result of the low recombination rate caused by the depletion of electrons in the p-base due to the negative V GC,ST . Figure 3c shows the energy band diagrams of 3-T TRAM at 10 ms after a program pulse to investigate the data retention characteristic depending on V GC,ST . The left side is for V GC,ST = 0.0 V, and the right side is for V GC,ST = − 0.4 V. The H P difference between the state-0 and state-1 at 10 ms after a program pulse exhibits a high value of 0.17 eV with the optimized V GC,ST of − 0.4 V due to the long-lasting N P . This indicates that the device with an optimized V GC,ST has an improved data retention characteristics that can maintain the lowresistance state (state-1) for a longer time. Figure 4a shows I A − V AC characteristics for the V AC pulse with T rise of 1000 s, T hold of 2 ns and T fall of 1000 s when V GC is fixed at − 0.4 V. It has been previously reported that the I A − V AC curve with long T fall of 1000 s can effectively provide a minimum V AC,ST to improve the data retention characteristics [12]. When V GC is fixed to − 0.4 V, the device exhibits a rapid increase of I A at V AC = 2.65 V representing a switching from the state-0 to the state-1. This indicates that a higher V AC is required to switch the state as long as V GC is maintained below − 0.4 V, and thus the state is well protected. As mentioned above, for a normal programming, only 1.2 V of V AC,P is required since V GC is increased from − 0.4 to 0.4 V. As such, for V AC,P less than 2.6 V applied to the bit line (BL) in array operation, 3-T TRAM can avoid unwanted program errors if the voltage of the word line (WL) is fixed to V GC,ST = − 0.4 V or below.

Optimization of Standby Voltages
In the downward V AC sweep (T fall ), the switching of the state occurs at 0.56 V as evidenced by the sharp slope (red dashed line in Fig. 4a). Thus, the state-1 can be maintained at V AC,ST of 0.56 V. To investigate this drastic change by the voltage difference as small as 0.1 V, N P as a function of T ST,1 is examined for two different V AC,ST of 0.5 V and 0.6 V (Fig. 4b). For V AC,ST = 0.5 V, the stored holes disappear rapidly after 10 μs, but for V AC,ST = 0.6 V, the device can maintain a high N P of about 1.47 × 10 18 cm −3 for more than 10 s which is 10 6 times larger. Figure 4c   the holes injection is not enough to compensate the loss of holes by recombination, and the stored charge rapidly disappears, returning the band shape back to that of the state-0. A device with V AC,ST lower than 0.5 V will face similar level or faster charge loss. Considering the clock speed of modern VLSI circuit, the 3-T TRAM with V AC.
ST of 0.6 V can exhibit the continuous state-1 virtually without a refresh operation. In addition, despite the high V AC,ST of 0.6 V, the device has a standby current as low as 1.14 pA, suggesting that the 3-T TRAM with the V AC,ST of 0.6 V is suitable for a low-power operation.

Memory Operation of 3-T TRAM Array
Compared to the 2-T TRAM without the gate terminal, the 3-T TRAM has a strong state immunity against the change of anode-cathode potential by controlling the storage potential with the gate terminal. On the other hand, the shift in gate-cathode potential in the 3-T TRAM easily interferes with the stored information. This disturbance is studied by assuming an operation pulse applied to a nearby cell. The cell under the study is initially at unselected bias condition, and the subject cell's states after the disturbance are observed. Figure 5 shows the schematic of a memory-cell-array configuration of 3-T TRAM. Our study shows that, with a proper operating scheme (maintaining fixed V GC to the unselected cells), this memory-cell-array configuration can prevent unselected cells' unwanted changes. For an efficient adjustment of V GC in the memory operation, the gate and cathode electrodes are set to the WL and BL, respectively. The anode electrode is fixed at 0.6 V. Table. 1 shows the operating voltage conditions for the 3-T TRAM array.

Fig. 5 Schematic diagram of the 3-T TRAM memory-cell-array configuration
To maintain the stable state-0 and state-1 in the standby state, V G and V C in the standby state are set to − 0.4 V and 0.0 V with the V A of 0.6 V. The operation strategies to prevent the array disturbance, found through our study, are summarized for each operation (program, erase and parallel read) as the followings.
Program: To program the selected cell, the selected V C decreases from 0.0 to − 0.8 V as shown in Table 1. This decreased V C can facilitate the influx of carriers into the base region. As such, the selected cell is programmed with the V GC of 0.4 V and V AC of 1.4 V. Figure 6a  Erase: To erase a selected cell, the V G and V C of the selected WL and BL should be increased from − 0.4 to 0.8 V and 0.0 to 0.4 V, respectively, as shown in Table 1. In Fig. 7a, the N P is investigated as a function of T ST,0 after the erase operation at T ST,1 of 2.5 ns. The N P is decreased due to the depletion of stored holes in the p-base as the V GC increases from − 0.4 to 0.4 V. Also, the hole injection into the p-base during the erase operation is restrained by decreasing V AC from 0.6 to 0.2 V. As the T ST,0 increases, the N P is back to 0 cm −3 , which represents the complete state-0. To investigate the reason, the energy band diagram at T ST,0 of 2.5 ns is examined and compares with the energy band at T ST,1 of 2.5 ns (Fig. 7b). After the erase operation, the n-base (H N ) energy band height decreases as the H P increases. The holes in the anode flow into the p-base over the lowered H N and the N P increase. The number of injected holes decreases due to the increased H N by the recombination process, so the N P saturates at 0 cm −3 as T ST,0 increases. From this result, it is found that the cell selected for the erase operation can exhibit the state-0 with the sufficiently high H P at any T ST,0 . However, the erasing method with the increased V GC of the selected WL can cause a problem of erasing all cells on the same WL. To avoid this issue, the V GC should be reduced from 0.4 to − 0.4 V by increasing V C from 0.0 to 1.2 V on all BLs except for the selected BL (Table 1). Accordingly, the erase disturbance pulse with V AC = − 0.6 V and V GC = − 0.4 V applies to the unselected cells on the same WL. The state-1 should be detectable at any time even if this erase disturbance pulse is repeated after the N P is saturated to the lowest value of 1.47 × 10 18 cm −3 . To confirm this, as shown in Fig. 7c, the N P is examined as a function of the number of this erase disturbance pulse. Despite the repeated disturbance pulses, N P exhibits a negligible decrease near 1.1 × 10 18 cm −3 so that the device can maintain the state-1. In addition, the slightly reduced N P can readily return Table 1 Operating voltage condition of 3-T TRAM  to its original state-1 by applying read operation. Therefore, the 3-T TRAM can overcome the erase disturbance by controlling the V GC in unselected cells, Parallel Read: To perform the parallel read operations on the cells that share the same BL, the V C of the selected BL and the V G of all WLs are set to − 0.8 V (Table 1). If the V C in the selected BL is decreased to − 0.8 V, not only V AC increases to 1.4 V but also V GC increases to 0.4 V. This high V GC lowers the H P and causes unwanted program errors of the cells in the selected BL. To avoid this, the V G in all WLs should be decreased to − 0.8 V so that 0.0 V of V GC and 1.4 V of V AC are applied to the cells in the selected BL. To investigate the effect of the read operation on the state-0, the operating voltage and anode current are extracted after ten consecutive read operations are applied following an erase operation as shown in Fig. 8a. Although the ten continuous read pulses are applied to the device after the erase operation, the read current gradually decreases, confirming that the state-0 stably is maintained. This result indicates that the 3-T TRAM with the suggested array configuration for reading exhibits a reliable disturbance immunity for the state-0.  Additionally, to confirm the detectability of the state-1, the operating voltage and anode current for a program and a read with the T ST,1 of 10 s are extracted (Fig. 8b). The read pulse can detect the state-1 continuously with a high current even at a long T ST,1 of 10 s.

Conclusion
We have investigated the effects of the V GC,ST and V AC,ST of the nanoscaled 3-T TRAM for low-power operation and better retention characteristics. The optimized V GC,ST of − 0.4 V allows a lower V AC,P due to the accumulated holes in the standby state. In addition, a low H P remains for a longer time because the optimized V GC,ST effectively maintains the high N P by reducing carrier recombinations at the junctions. The investigation of I A − V AC characteristics suggests that a minimum V AC,ST of 0.6 V enables the device to exhibit the continuous state-1 without refresh operation while allowing a small standby current of 1.14 pA. Furthermore, a memory array operation strategy with the proper V GC,ST and V AC,ST for the 3-T TRAM is presented for the first time to implement reliable array operations without refresh and disturbances. The adjustment of V GC can effectively minimize the program, erase and read disturbances in unselected cells. Along with the high immunity against array disturbances, the 3-T TRAM with the optimum strategy for array operations exhibits superior data retention capability than conventional 1T-1C DRAM technology. Thus, the proposed memory array operation scheme can provide a way to realize capacitorless 1T DRAM with 3-T TRAM.