- Special Issue Article
- Open Access
Mold Fabrication for 3D Dual Damascene Imprinting
© The Author(s) 2010
- Received: 11 September 2009
- Accepted: 16 January 2010
- Published: 30 January 2010
Previously, a damascene process based on nanoimprint lithography has been proposed (Schmid G M, et al. in J Vac Sci Technol B 24(3) 1283, 2006) to greatly reduce the fabrication steps of metal interconnection in integrated circuit. For such a process to become a viable technique, a mold having two pattern levels with precise alignment between them must be fabricated first. To this end, this work demonstrates a “self-aligned” fabrication process where the two pattern levels would be perfectly aligned if ignoring the noise during e-beam writing. The process is based on one EBL on a bi-layer resist stack, with the sensitivity for the top layer much higher than that of the bottom layer, which enables separate pattern transfer of the two pattern levels. Using ZEP-520A and poly(dimethylglutarimide) (PMGI) resists, we fabricated pillars having a diameter of 150 nm sitting on ridges having a width of 1.5 μm, which can be used to create via-holes and trenches for IC interconnect by nanoimprint lithography. The current process can also find applications in other areas that require two-level patterning with precise alignment between them.
- Electron beam lithography
- Nanoimprint lithography
An advanced integrated circuit (IC) typically has eight or more wiring levels, each of which consists of metal via and line structures. The metal lines distribute signals within each interconnect level, whereas metal vias transmit signals between the adjacent wiring levels. In state-of-the-art ICs, copper is used as the interconnect material due to its higher conductivity than Al. Owing to the lack of a well-established plasma etching process for Cu, dual damascene process is adopted to fabricate Cu interconnect except for the first wiring level where tungsten CVD plug is used. In a dual damascene process, in order to significantly reduce the process steps, vias and lines are fabricated simultaneously by Cu electroplating and chemical mechanical polishing. However, it still needs more than twenty process steps to fabricate each wiring level using dual damascene process .
In a recent work, Schmid et al.  proposed a damascene process based on imprint lithography to fabricate metal interconnect. Via-holes and trenches are created in a single imprint step using a mold having two pattern levels consisting of pillars sitting on top of ridges. When imprintable dielectric material is used as a UV-curable imprint resist, the number of steps of such a process is only one-third that of the standard photolithography-based dual damascene process. However, for the imprint damascene process to become a practical manufacturing method, one-first needs to fabricate a 3D imprint mold (template) with acceptable overlay error between the two pattern levels. This is not trivial because, unlike projection optical lithography where 4× reduction is used, imprint is a 1× process where the overlay error in the mold will be transferred to the resist without any error reduction.
The mold in Ref.  has been fabricated by electron beam lithography (EBL) with two resist exposures for the two pattern levels. In this work, we will demonstrate a mold fabrication technique by EBL where the two levels of mold structures are exposed in the same step using a bi-layer resist stack having different sensitivities. The structures are therefore “self-aligned” with each other with negligible overlay error. In addition to improved alignment accuracy, the process consists of fewer steps than previous mold fabrication process that involves two EBL steps and two pattern transfer steps by etching. Moreover, in the previous process, the resist for the second pattern level is spun on a non-flat surface consisting of features of the first pattern level, which leads to resist film thickness non-uniformity and process error unless a dry evaporated resist is used [3, 4]. This problem is not an issue for the current process since the bi-layer resists are spun on a flat wafer surface one after the other. Besides semiconductor device interconnect, the current method can be extended to other applications requiring two-level patterning with precise alignment between them.
Here we have chosen the resist combination as ZEP-520A (from Zeon Corp.) with sensitivity ~50 μC/cm2 for the top layer, and poly(dimethylglutarimide) (PMGI, from MicroChem Corp.) with sensitivity ~1,000 μC/cm2 for the bottom layer. In addition to the large difference in sensitivity, ZEP-520A can be dissolved by anisole for metal liftoff, which does not attack the bottom PMGI layer. PMGI is not a typical EBL resist. Instead, it is commonly used as a liftoff resist in a bi-layer stack with PMGI as the bottom layer , because its chemistry is “orthogonal” to that of common EBL resist like ZEP-520A (and PMMA): on the one hand, it is resistant to most solvents that dissolve ZEP-520A, which is essential for spin-coating the bi-layer resist stack; on the other hand, it is dissolved (etched laterally when underneath ZEP-520A) by base solutions consisting of KOH or tetramethylammonium hydroxide (TMAH), which does not attack the top ZEP-520A layer. As the dissolution rate by a base solution increases drastically when PMGI is exposed to electrons, it is effectively an EBL resist with sensitivity of 50–100 μC/cm2[6, 7]. However, its sensitivity drops considerably to ~1,000 μC/cm2 when using solvent developers such as methyl ethyl ketone (MEK) and methyl isobutyl ketone (MIBK) , making it a suitable choice for the current bi-layer resist process. The rather low sensitivity of PMGI does not increase the e-beam writing time significantly because the exposure area of the pillars is much less than that of the trenches.
Compared to the previous process for the fabrication of an imprint mold having two pattern levels, which involves two EBL steps, two metal liftoffs, and two etchings, the current process consists of only one EBL step, one metal liftoff, and two etchings; thus, it greatly reduces the mold fabrication cost and increases the throughput at the same time. In addition, using one EBL step on a bi-layer resist stack, a more straightforward fabrication procedure would consist of (after EBL) developing the top layer, metal deposition and liftoff, and RIE to define the ridge pattern; removing the metal and repeating the process steps to define the pillar pattern. Such a process involves two metal depositions and liftoffs, whereas the current one contains only one metal deposition step, so is simpler. It can achieve the desired result because SiO2 etching using CF4 gas is highly anisotropic, leading to negligible etch of the SiO2 surrounding the Cr “disk” on the substrate. Otherwise, a more isotropic etching chemistry using SF6 gas would result in a ring-shaped pattern surrounding the Cr “disk” .
For the resist selection, we have used two positive resists ZEP-520A and PMGI. Resist combination of PMMA and PMGI could also be used to fabricate the mold, yet the process window would be narrower since the sensitivity difference between PMMA and PMGI is smaller. In addition, acetone, the most common solvent for liftoff, cannot be used here because it was found that PMGI can be dissolved by acetone once it is exposed to electrons with the dissolution rate depending on the exposure dose. Therefore, we have chosen anisole for Cr liftoff, which was found not to attack PMGI noticeably even when it is exposed to electrons. Lastly, besides positive resist combinations, in principle, one can also use negative resists (one negative and one positive, or both negative) by carrying out the pattern transfer using RIE with the resist as etching mask. Such a process involves fewer steps as no metal deposition and liftoff is needed, though the process would be limited by the etching selectivity between the resist and SiO2.
Finally, though we have succeeded in fabricating the mold having two pattern levels, the current process is not expected to be able to completely replace the conventional process involving two EBL steps. For instance, it would be difficult using the current process to fabricate a two-level structure where the top (fine) features are not located far away from the edge of the bottom (large) features, as otherwise the edge would be overexposed due to proximity effect that results in a poorly defined feature edge. The current process is also not capable of fabricating a two-level structure where the features of the “top” level sit inside the trenches (rather than on top of the ridges) of the “bottom” level. Such a structure can only be fabricated using the conventional method involving two separate EBL steps, as demonstrated in Ref .
We have demonstrated the fabrication of nanoimprint lithography molds having two pattern levels that can be used for the patterning of via-holes and trenches for IC interconnection. The process involves only one EBL step on a bi-layer resist stack, so the alignment between the two levels would be perfect if ignoring the noise during e-beam writing. For such a process to work properly, the two resists must have very different sensitivity; and their chemistry should be ideally “orthogonal”—the liquid (solvent or aqueous solution) that dissolves one resist should not attack the other resist. Using ZEP-520A and PMGI as the top and bottom layer resists, we fabricated an imprint mold consisting of 150-nm diameter pillars sitting on top of 1.5 μm—wide ridges. Other resist combinations, including negative resists, may also be used for the fabrication. The current process can be extended to other applications requiring two-level patterning with precise alignment between them.
This article is distributed under the terms of the Creative Commons Attribution Noncommercial License which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.
- MacDonald S, Hughes G: Proc SPIE. 2005. 5992 59922F 5992 59922FGoogle Scholar
- Schmid GM, Stewart MD, Wetzel J, Palmieri F, Hao J, Nishimura Y, Jen K, Kim EK, Resnick DJ, Liddle JA, Willson CG: J. Vac. Sci. Technol. B. 2006, 24(3):1283. COI number [1:CAS:528:DC%2BD28XlvFWjt7o%3D] COI number [1:CAS:528:DC%2BD28XlvFWjt7o%3D] 10.1116/1.2197508View ArticleGoogle Scholar
- Kelkar PS, Beauvais J, Lavallee E, Drouin D, Cloutier M, Turcotte D, Yang P, Lau KM, Legario R, Awad Y, Aimez V: J. Vac. Sci. Technol. A. 2004, 22(3):743. COI number [1:CAS:528:DC%2BD2cXkt1Kmu70%3D]; Bibcode number [2004JVST...22..743K] COI number [1:CAS:528:DC%2BD2cXkt1Kmu70%3D]; Bibcode number [2004JVST...22..743K] 10.1116/1.1667503View ArticleGoogle Scholar
- Beauvais J, Lavallee E, Zanzal A, Drouin D, Lau KM, Veres T, Cui B: Proc. SPIE. 2005, 5751: 392. COI number [1:CAS:528:DC%2BD2MXlvFahs7c%3D]; Bibcode number [2005SPIE.5751..392B] COI number [1:CAS:528:DC%2BD2MXlvFahs7c%3D]; Bibcode number [2005SPIE.5751..392B] 10.1117/12.599795View ArticleGoogle Scholar
- Chen Y, Peng K, Cui Z: Microelectro. Eng.. 2004, 73–74: 278. COI number [1:CAS:528:DC%2BD2cXktF2ntL0%3D] COI number [1:CAS:528:DC%2BD2cXktF2ntL0%3D] 10.1016/S0167-9317(04)00111-XView ArticleGoogle Scholar
- Takano H, Nakano H, Minami H, Hosogi K, Yoshida N, Sato K, Hirose Y, Tsubouchi N: J. Vac. Sci. Technol. B. 1996, 14(6):3483. COI number [1:CAS:528:DyaK2sXht1ynsQ%3D%3D] COI number [1:CAS:528:DyaK2sXht1ynsQ%3D%3D] 10.1116/1.588784View ArticleGoogle Scholar
- Cord B, Dames C, Berggren KK, Aumentado J: J. Vac. Sci. Technol. B. 2006, 24(6):3139. COI number [1:CAS:528:DC%2BD2sXpt1Sksg%3D%3D] COI number [1:CAS:528:DC%2BD2sXpt1Sksg%3D%3D] 10.1116/1.2375090View ArticleGoogle Scholar
- Cui B, Veres T: Microelectro. Eng.. 2008, 85: 810. COI number [1:CAS:528:DC%2BD1cXmt1yitbc%3D] COI number [1:CAS:528:DC%2BD1cXmt1yitbc%3D] 10.1016/j.mee.2008.01.008View ArticleGoogle Scholar
- Ocola LE, Stein A: J. Vac. Sci. Technol. B. 2006, 24(6):3061. COI number [1:CAS:528:DC%2BD2sXpt1Smtw%3D%3D] COI number [1:CAS:528:DC%2BD2sXpt1Smtw%3D%3D] 10.1116/1.2366698View ArticleGoogle Scholar
- Cui B, Veres T: Microelectron. Eng.. 2007, 84: 1544. COI number [1:CAS:528:DC%2BD2sXkvFCrtLw%3D] COI number [1:CAS:528:DC%2BD2sXkvFCrtLw%3D] 10.1016/j.mee.2007.01.158View ArticleGoogle Scholar