Figure 9
Schematic illustration of nanotetrapod transistor and images of CdS nanotetrapod and the fabricated device. (a) Schematic illustration of a nanotetrapod transistor with a 300-nm-thick ferroelectric dielectric under testing with scanning tunneling microscope (STM) tips. The source (S) and drain (D) electrodes are the patterned Pt layer. (b) Typical TEM image of the multiarmed CdS nanotetrapod used in this study. (c) The enlarged micrograph of a single CdS nanotetrapod. (d) SEM image of a single CdS nanotetrapod device. (e) In situ SEM image of two STM tips (shown in white) probing on a testing device.