- Nano Express
- Open Access
Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique
© Su et al.; licensee Springer. 2012
Received: 30 November 2011
Accepted: 22 June 2012
Published: 22 June 2012
In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n+-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications.
With the aggressive downscaling of transistor dimensions to increase the speed and density of transistors on an integrated circuit, nanowire (NW) field-effect transistors (FETs) are considered as one of the most promising device architectures to meet the requirements [1–3]. Hence, a plethora of researches focusing on NW-based devices especially with multiple-gated structure has been widely explored [3–6]. Owing to the inherent tiny volume of NW, it enables better gate controllability for overcoming the short-channel effects over the planar FETs because the electrostatic potential in the ultrathin channel can be effectively controlled so that the channel suffers less electrical interference from the drain [3, 5]. Concurrently, the control on junction doping profiles of source/drain (S/D)-to-channel regions becomes extremely challenging in nanoscale regimes. In line with this, junctionless (JL) devices have been proposed to cope with the doping profile issue [7, 8]. In a JL structure, the dopant type and concentration are the same all the way from the source, channel to drain. Such JL transistor is operated as an accumulation-mode device and basically a gated resistor in the on-state, while it can be switched off by full depletion of carriers in the channel by the gate. Since no conventional p-n junctions are formed in it, the JL scheme can relieve the stringent formation technique of the ultra-shallow or ultra-abrupt junction, thus simplifying the fabrication process. Furthermore, the conduction mechanism of such scheme is via currents passing through the body of the channel, and accordingly, the most important criteria of this scheme is that the channel layer must be thin enough so it can be entirely depleted by the potential difference exerted by the gate . In this work, we present a junction-free NW device with gate-all-around (GAA) TiN/Al2O3 stack using one in situ doped poly-Si material for both the channel and S/D regions without any implant process. Due to the GAA structure together with the small body, the gate is capable of depleting the heavily doped channel thoroughly to switch the device off, thus obtaining a high on/off current ratio as well as good on-state performance. In addition, most high-κ oxides have positive fixed charges, except that Al2O3 has negative fixed charges . By taking advantage of this feature, we investigate the utilization of Al2O3 as the gate dielectric for the n+-poly-Si channel device and expect that the proposed JL device could be desirably operated in a positive threshold voltage (Vth) range for favoring its applications in logic circuits and memory devices.
Device fabrication and experiment
In this study, Hall measurements were conducted on a blanket in situ doped poly-Si thin film of 3,000 Å; the carrier concentration of PH3 with 15 sccm flow rate was found to be around 1 × 1020 cm−3. However, the practical active carrier concentration in the NW channels of the fabricated devices would be much lower than the result of Hall measurements due to the effects of film volume  and donor deactivation occurring in the Si NW structure .
Results and discussion
In summary, we have reported the fabrication and experimental investigation of the junction-free GAA NW device with TiN/Al2O3 gate stack structure by employing an implant-free method. From the results of the electrical characterizations, a sufficiently small cross section of the NW channels is essential to obtain superior on/off current ratio for heavily doped channel devices. The fabricated DC devices also show excellent Vth roll-off properties and boosted on-state performance especially as the channel length increases. The adoption of Al2O3 as the gate dielectric shifts the Vth to a positive value and thus is conducive to acquiring desirable Vth. With its low cost and straightforward processing, we believe that the proposed GAA NW JL transistor architecture is promising for future 3-D electronics and system-on-panel applications.
The authors would like to thank the National Nano Device Laboratories (NDL) and Nano Facility Center (NFC) of National Chiao Tung University for assistance in device fabrication. This work was supported in part by the Ministry of Education in Taiwan under Aim for the Top University (ATU) Program and in part by the National Science Council of the Republic of China under contract No. 99-2221-E-009-167-MY3.
- Yeo KH, Suk SD, Li M, Yeoh YY, Cho KH, Hong KH, Yun S, Lee MS, Cho N, Lee K, Hwnag D, Park B, Kim DW, Park D, Ryu BI: Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In International Electron Devices Meeting: December 11–13 2006. IEEE, San Francisco. Piscataway; 2006:1–4.View ArticleGoogle Scholar
- Appenzeller J, Knoch J, Björk MT, Riel H, Schmid H, Riess W: Toward nanowire electronics. IEEE Trans Electron Devices 2008, 55: 2827.View ArticleGoogle Scholar
- Suk SD, Li M, Yeoh YY, Yeo KH, Ha JK, Lim H, Park HW, Kim DW, Chung TY, Oh KS, Lee WS: Characteristics of sub-5-nm trigate nanowire MOSFETs with single- and poly-Si channels in SOI structure. In VLSI Symposium Technology: June 16–18 2009; Honolulu. IEEE, Piscataway; 2009:142.Google Scholar
- Singh N, Agarwal A, Bera LK, Liow TY, Yang R, Rustagi SC, Tung CH, Kumar R, Lo GQ, Balasubramanian N, Kwong DL: High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett 2006, 27: 383.View ArticleGoogle Scholar
- Im M, Han JW, Lee H, Yu LE, Kim S, Kim CH, Jeon SC, Kim KH, Lee GS, Oh JS, Park YC, Lee HM, Choi YK: Multiple-gate CMOS thin-film transistor with polysilicon nanowire. IEEE Electron Device Lett 2008, 29: 102.View ArticleGoogle Scholar
- Hsu HH, Lin HC, Luo CW, Su CJ, Huang TY: Impacts of multiple-gated configuration on the characteristics of poly-Si nanowire SONOS devices. IEEE Trans. Electron Devices 2011, 58: 641.View ArticleGoogle Scholar
- Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R: Nanowire transistors without junctions. Nature Nanotechnol 2010, 5: 225. 10.1038/nnano.2010.15View ArticleGoogle Scholar
- Su CJ, Tsai TI, Liou YL, Lin ZM, Lin HC, Chao TS: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett 2011, 32: 561.Google Scholar
- Wilk GD, Wallace RM, Anthony JM: High-κ gate dielectrics: current status and materials properties considerations. J Appl Phys 2001, 89: 5243. 10.1063/1.1361065View ArticleGoogle Scholar
- Lacy F: Developing a theoretical relationship between electrical resistivity, temperature, and film thickness for conductors. Nanoscale Research Lett 2011, 6: 636. 10.1186/1556-276X-6-636View ArticleGoogle Scholar
- Björk MT, Schmid H, Knoch J, Riel H, Riess W: Donor deactivation in silicon nanostructures. Nature Nanotechnol 2009, 4: 103. 10.1038/nnano.2008.400View ArticleGoogle Scholar
- Lee CW, Lederer D, Afzalian A, Yan R, Dehdashti N, Xiong W, Colinge JP: Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs. Solid State Electron 1815, 2008: 52.Google Scholar
This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.