High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure
© Chen et al.; licensee Springer. 2012
Received: 8 December 2011
Accepted: 26 April 2012
Published: 1 August 2012
A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.
Since the transistor speed in circuit consideration is very impressive, III-V compound semiconductors can be treated as potential channel replacement materials for Si in deep nanoprocess integration. III-V materials such as GaAs and InAs possessing higher electron mobility are expected to conduct higher drive current. Conventionally, operation of III-V field-effect transistors (FETs) mainly relies on a Schottky gate structure to modulate channel potential. However, the Schottky gate suffers from high leakage current issue which restrains III-V devices from very-large-scale integration. Metal-oxide-semiconductor (MOS) gate structure used in Si MOSFET is thermodynamically stable and effective for leakage current reduction. In contrary, the lack of a high-quality oxide/semiconductor scheme has limited the applications of III-V devices for decades. Recently, several groups have demonstrated encouraging results in aspects of III-V surface cleaning or pretreatment methods[2, 3], growth of insulator on various III-V materials[4, 5], as well as realization of III-V MOSFETs[6–11]. Up-to-date III-V MOSFET technologies have demonstrated significant performance enhancement and have achieved low gate leakage[8, 10], high channel mobility[7, 11], and high drive current. Consequently, it is feasible to produce high-performance MOSFETs using III-V materials. On the other hand, when the scaling of planar Si complementary-symmetry metal-oxide-semiconductor (CMOS) gradually approaches its physical limit, three-dimensional fin-shaped FET (FinFET) device architecture[12–15] is a promising alternate enabling transistor scaling beyond the 22-nm technology node. FinFET structure provides superior control of short channel effects; however, there are only few reports on III-V-based FinFETs[15, 17, 18]. In this letter, for the first time, a novel III-V MOSFET device technology based on a three-dimensional FinFET structure is reported. Al2O3 film is used as the gate insulator, and submicron GaAs fin is the channel. Both III-V MOSFET and metal–semiconductor FET (MESFET) with a FinFET structure were fabricated, characterized, and evaluated.
Results and discussion
Electrical performance of 3D III-V nMOSFET and nMESFET with 0.6-μm gate width and 0.5-μm length
2.54 × 105
1.17 × 102
Ion (μA) at VGS = VDS = 1 V
Vth (V) at VDS = 0.1 V
SS (mV/decade) at VDS = 1 V
SS (mV/decade) at VDS = 0.1 V
I on/I off, on current/off current; V GS, gate voltage; V DS, drain voltage; V th, threshold voltage; SS, subthreshold swing; DIBL, drain-induced barrier lowering; MOSFET, metal-oxide-semiconductor field-effect transistor; MESFET, metal–semiconductor field-effect transistor.
Measurement and analysis of high-performance III-V nMOSFET are achieved by applying a FinFET structure to device fabrication. The device exhibits excellent subthreshold characteristics and demonstrates significant performance improvement over conventional Schottky gate nMESFET or planar III-V nMOSFETs because of the enlarging channel width, the existing higher channel electron mobility compared with silicon channel and lower channel interface states, as well as the good gate controllability representing the smaller swing value. The three-dimensional III-V nMOSFET device technology developed illustrates great potential and is promising when the CMOS technology is pushed toward more stringent scaling in the foreseeable future.
SHC is an associate researcher at National Nano Device Laboratories, Hsinchu, 30078, Taiwan. WSL is a full professor in the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. HCY is an assistant professor in the Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, 30401, Taiwan. SJW is an assistant professor in the Department of Materials and Resources Engineering, National Taipei University of Technology, Taipei, 10608, Taiwan. YGL is the vice president of ADATA Technology Company, New Taipei, 23553, Taiwan. HW is a distinguished professor from the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. HSG is a full professor in the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. MCW is a full professor in the Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, 30401, Taiwan.
The authors would like to thank the National Nano Device Laboratories in Hsinchu, Taiwan for the experimental sample preparation.
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