# Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

- Michael Loong Peng Tan
^{1, 2}Email author, - Georgios Lentaris
^{2}and - Gehan AJ Amaratunga
^{2}

**7**:467

https://doi.org/10.1186/1556-276X-7-467

© Tan et al.; licensee Springer. 2012

**Received: **29 June 2012

**Accepted: **9 August 2012

**Published: **19 August 2012

## Abstract

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (*I*_{on}/*I*_{off}), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

### Keywords

Device modeling HSPICE Benchmarking MOSFET CNTFET Logic gates## Background

Carbon nanotubes (CNTs) have been proposed as an alternative channel material to silicon (Si), based on their quantum transport properties which, in principle, allow ballistic transport at room temperature. CNT ballistic modeling[1] has been used to assess the performance of the device at the HSPICE circuit level[2]. Device modeling is vital for projecting the practical performance of a CNT transistor as a switching device in integrated circuits (ICs).

We report the potential of a CNT channel through modeling as a substitute to a silicon channel in a scaled metal-oxide-semiconductor field-effect transistor (MOSFET) for logic applications. By scaling the Si transistor and the density of states (DOS) of the CNT, we observe good agreement between CNT and ballistic Si MOSFET[3] in the drain current–voltage (*I* *V*) output characteristics. Output current is critical in determining the switching speed of a transistor in logic gates. We show that the output performances of CNT and Si channel devices are similar in the 45-nm node experimental data. However, the modeling results point to significant reduction in drain-induced barrier lowering (DIBL) and related high field effects in the CNT compared to the short-channel nanoscale Si MOSFET at the same output current. We also assess the effect of channel area restructuring on electric field properties as well as the role of the DOS in determining CNT current. Unlike in the Si MOSFET, it is seen that the performance of a CNT channel is enhanced when the source/drain width is minimized rather than the channel length due to gate-to-source/drain parasitic fringe capacitances. MOSFET scaling according to Moore's law is limited by process controllability.

## Methods

### Carbon nanotube and MOSFET modeling

*W*) of the source and drain contacts and the length (

*L*) of the nanotube. Details of the ballistic MOSFET modeling can be found in our previous work[3].

**Source and drain capacitance for multiple substrate insulator thickness**

Substrate insulator thickness (nm) | C | I |
---|---|---|

10 | 34.53 | 47.395 |

50 | 6.906 | 47.340 |

100 | 3.453 | 47.272 |

200 | 1.727 | 47.135 |

300 | 1.151 | 46.998 |

400 | 0.863 | 46.860 |

500 | 0.691 | 46.723 |

If a CNT can achieve the same current as a MOSFET, an identical channel area (*A*_{MOS} = *A*_{CNT}) can be maintained by setting the width of the physical space occupied by the CNTFET to be *W*_{CNT} = *A*_{MOS} / *L*_{CNT}. When *W* = *L* for the MOSFET, the general channel area can be expressed as *A* = (*kL*)^{2}, where *k* is the scaling factor. As such, a CNT channel with length, 2*kL* should attain the same current with *W* = 0.5*kL*. Thus, if the physical width of the CNT channel is *W* ≤ 0.5*kL*, there will not be any area drawback in output current due to the longer *L*. In fact, the maximum electric field in CNT is halved, giving *E*_{mCNT} = *E*_{mSi} / 2, and is significantly reduced as the CNT channel grows longer. For a CNT with *L* = 60 nm compared to a Si MOSFET with *L* = 45 nm, the maximum electric field is *E*_{m} = 0.83 *E*_{mSi}.

### Device modeling

*S*= 20 nm,

*C*= 60 nm, and

*W*

_{C}=

*L*

_{C}= 100 nm. Nine capacitances are introduced into the carbon-based macromodel as illustrated in Figure3. They are the gate oxide capacitance

*C*

_{ox}, quantum capacitance

*C*

_{Q}, source capacitance

*C*

_{s}, drain capacitance C

_{d}, substrate capacitance

*C*

_{sub}, source-to-bulk capacitance

*C*

_{sb}, drain-to-bulk capacitance

*C*

_{db}, gate-to-source capacitance

*C*

_{gs}, and gate-to-drain capacitance

*C*

_{gd}. The size of the contact is crucial as it ultimately influences

*C*

_{sb}and

*C*

_{db}. They are given in Table1 and can be written as

*t*

_{ins}is the thickness of the insulator,

*W*is the width of the contact,

*L*is the length of the contact, and

*ε*

_{ins}is the permittivity of the insulator. The substrate insulator capacitance

*C*

_{sub}for CNTFET is given by

*t*

_{sub}is the substrate oxide thickness and

*d*is the diameter of CNT. The intrinsic gate capacitance

*C*

_{G}of CNTFET is a series combination of gate oxide capacitance

*C*

_{ox}and quantum capacitance

*C*

_{Q}[11]. The

*C*

_{ox}of a CNTFET[12–14] is shown to be

*g*

_{s}is the spin degeneracy,

*g*

_{v}is the valley degeneracy,

*E*

_{Gi}is the bandgap energy, and

*v*

_{F}is the Fermi velocity. The step function$\Theta \left(x\right)$ is equal to 1 when

*x*> 0 and 0 when

*x*< 0. The

*C*

_{gs}and

*C*

_{gd}are given as

where *C*_{s} and *C*_{d} are the source and drain capacitance fitting parameters, respectively,[1, 2] that are used to fit the experimental data and *L*_{g} is the length of the gate. The sum of *C*_{gd} and *C*_{db} gives the intrinsic capacitance *C*_{int}.

*I-V*formulation of short-channel MOSFET. Tan et al.[3] succinctly show the transformation of the square law that applies for the long channel to the linear law that is applicable for short-channel MOSFET. On the other hand,

*I-V*formulation for the CNTFET model follows the quantum conductance principle that was developed by Rahman et al.[4, 5] and Datta[6]. The

*I-V*model can be rewritten in terms of drain voltage

*V*

_{d}, source voltage

*V*

_{s}, and gate voltage

*V*

_{G}that is expressed by

where *G*_{ON} is the ON-conductance, *V*_{sc} is also known as the channel surface potential[11], *E*_{F} is the Fermi energy, *k*_{B} is the Boltzmann constant, *T* is the temperature, and *q* is the electric charge. The equation is iteratively solved and hence includes the effect of gate voltage.

### Model verification

*I*

_{on}/

*I*

_{off}ratio of two orders of magnitude lower than Si MOSFET. The quantum ON-conductance limit of a ballistic single-walled carbon nanotube (SWCNT) and graphene nanoribbon with perfect contact is

*G*

_{ON}= 4

*e*

^{2}/

*h*and

*G*

_{ON}= 2

*e*

^{2}/

*h*(twice the fundamental quantum unit of conductance), respectively

*.*Quantum capacitance

*C*

_{Q}is directly proportional to the density of states of the semiconductor but inversely proportional to the electrochemical potential energy. When

*C*

_{Q}becomes smaller than

*C*

_{ox}, a large quantity of the electrochemical potential energy is needed to occupy the states above the Fermi energy. This results in the reduction in overall intrinsic gate capacitance

*C*

_{G}and limits the channel charge in a semiconductor and ultimately the

*I*-

*V*characteristic of the FET devices. Comparison in Table2 shows that MOSFET has a higher cutoff frequency due to higher transconductance as compared to CNTFET with lower capacitances.

**Device model specification at** V _{
GS
} **= 1 V**

Parameter | CNTFET benchmarking | |
---|---|---|

CNTFET | MOSFET | |

Channel length, | 50 nm | 45 nm |

Contact width, | 100 nm | - |

Channel width, | - | 125 nm |

Channel area | 5 × 10 | 5.63 × 10 |

Nanotube diameter | 1.5437 nm | - |

Chiral vector [ | [20,0] | - |

Maximum current, | 46.56 μA | 50.20 μA |

Transconductance, | 68.1 μS | 148 μS |

Carrier density, | 30.16 μA/nm | 0.40 μA/nm |

Gate capacitance, | 14.85 aF | 65.8 aF |

Drain capacitance, | 0.59 aF | 19.0 aF |

Source capacitance, | 1.43 aF | 78.7 aF |

Substrate capacitance, | 1.60 aF | 6.52 aF |

Total terminal capacitance, | 18.47 aF | 209.02 aF |

Intrinsic capacitance, | 21.29 aF | 37.40 aF |

Load capacitance, | 46.54 fF | 50.13 fF |

Cutoff frequency with 5-μm wire | 13.57 GHz | 27.72 GHz |

Drain-induced barrier lowering | 40.85 mV/V | 83.89 mV/V |

Subthreshold swing | 72.3 mV/decade | 113.67 mV/decade |

On-off ratio | 2.99 × 10 | 9.54 × 10 |

First, MOSFET logic circuits are built based on a 45-nm generic PDK. The MOSFET designs are then compared with carbon-based circuit models that consist of prototype digital gates implemented in HSPICE circuit simulator. These CNTFETs use 45-nm process design rules, namely the minimum contact size. For a fair assessment, both MOSFET and CNTFET are designed to provide similar current strength (≈46 to 50 μA).

_{2}. Metal contacts were patterned by electron beam lithography, and 60 nm of palladium (Pd) contacts was deposited to form a back gate geometry transistor. The spacing between the Pd contacts varied between 56.6 nm and 1.06 μm as shown in Figure5.

A four-probe measurement was carried out at room temperature to extract the resistance characteristics of the carbon nanotube that was used to form the transistor channel. The normalized resistances were 0.495, 0.744, 0.118, and 0.450 MΩ/nm for *R*_{2,3}, *R*_{2,4}, *R*_{3,4}, and *R*_{4,5}, respectively, where indices indicate Pd contact labels. The diameter of the SWCNT is 1.5 nm. Calculation shows that the 415-nm nanotube resistance is 27.8 kΩ that is almost equal to the theoretical *R*_{ON} *= h/q*^{2} = 25.812 kΩ and four times larger than the theoretically lowest quantum resistance of the SWCNT, *R*_{ON} *= h/4q*^{2} = 6.5 kΩ.

Though at 415-nm channel length ballistic transport is not preserved in the CNT, it is still only factor 4 larger than the theoretically expected minimum, suggesting that scattering is not extensive. Nevertheless, the model which assumes ballistic transport predicts similar saturation current levels (≈50 μA) for both the 50- and 415-nm channel devices, as illustrated in Figure5. Practically, this suggests that one must have CNT channel lengths below approximately 100 nm or even low contact resistance in order to utilize ballistic transport in them.

## Results and discussion

### Circuit analysis

*I*-

*V*characteristics. The performance evaluation of these Boolean operations is listed in Table3.

**45-nm process propagation delay computation between CNTFET (with and without interconnect) and MOSFET (post-layout simulation)**

Logic circuits | CNTFET with 45-nm process design guidelines | MOSFET with 45-nm process | |
---|---|---|---|

Delay without interconnects | Delay with 5-μm interconnect | Delay (post-layout simulation) | |

Propagation delay, | Propagation delay, | Propagation delay, | |

t | t | t | |

NOT | 0.14 | 9.277 | 5.005 |

NAND2 | 0.39 | 12.97 | 8.719 |

NAND3 | 0.61 | 16.87 | 11.343 |

NOR2 | 0.47 | 12.98 | 8.797 |

NOR3 | 0.50 | 16.48 | 11.655 |

### Performance evaluation

*P*

_{av}is the average power and

*t*

_{p}is the propagation delay.

*L*

_{wire}= 5 μm. It increases to 1,000 times without interconnect (

*L*

_{wire}= 0 μm).

Table3 shows the average propagation delay, *t*_{p}, for logic gates NOT, NAND2, NAND3, NOR2, and NOR3 for CNTFET with and without interconnect in comparison with MOSFET during post-layout simulation. It is found that NAND3 or NOR3 has the largest propagation delay since both of them has multiple fan-in and fan-out each. In the digital logic simulation of CNTFET, we use an average length of 5 μm per fan-out.

## Conclusions

We have established that a longer channel CNT is capable of delivering output currents comparable to those from a 45-nm-node Si MOSFET. This is possible due to the preservation of ballistic transport over distances approaching 100 nm and the higher current density of a single CNT forming the channel. Consequently, in the same practical channel area, a CNT allows reduction of short-channel effects as it has a lower *E*_{max}, leading to a lower DIBL and off current.

Devices with thicker substrate insulator and smaller source drain contact area give the highest frequency. In addition to that, logic gates NOT, NAND2, NAND3, NOR2, and NOR3 and their corresponding input and output waveforms are given. The interconnect length of cascading logic gates has a profound effect on the signal propagation delay. In the digital logic simulation, the key limiting factor for high-speed CNT-based chips is the interconnect itself. The performance enhancement of these carbon-based material is negligible if the interconnect capacitance is not reduced significantly with transistor feature size. Bundled metallic MWCNTs are seen as a potential candidate to replace copper interconnects as future IC interconnects once the challenges of integrating CNT interconnects onto existing manufacturing processes are met.

We also show that ballistic transport is not maintained in a CNT when contact resistance is large. A good fit to the data output characteristics from a 50-nm CNT channel device is obtained. As mean free path in a CNT is very long, often exceeding 1 μm, the ballistic process plays a predominant role, similar to one discussed extensively by Riyadi and Arora[19]. In fact, they define a new feature, named ballisticity. The truly ballistic transport is possible as channel length approaches zero. In a finite length, there are always finite probabilities of scattering.

## Authors’ informations

MLPT was born in Bukit Mertajam, Penang, Malaysia, in 1981. He received his B. Eng. (electrical-telecommunication) and M. Eng. (electrical) degrees from Universiti Teknologi Malaysia (UTM), Skudai, Malaysia, in 2003 and 2006, respectively. He conducted his postgraduate research in nanoscale MOSFET modeling at the Intel Penang Design Center, Penang, Malaysia. He recently obtained his Ph.D. degree in 2011 at the University of Cambridge, Cambridge, UK. He is a senior lecturer at UTM. His present research interests are in device modeling and circuit simulation of carbon nanotube, graphene nanoribbon, and MOSFET. MLPT is an IEEE member, member of IET (MIET), graduate member of IEM (GRAD IEM), and member of Queens' College. GL was born in Chania, Crete, Greece in 1983. He holds a B. Eng. (computing and robotic systems) degree from the Department of Electric Engineering in Liverpool University and a Ph.D. degree in engineering from the University of Cambridge. His Ph.D. thesis was in the area of fabricating and characterizing single-walled carbon nanotubes and ZnO nanowire transistors and sensors. He has also worked as a researcher at Nokia's Eurolab between 2009 and 2011 and particularly in developing novel sensors as part of Nokia's Nanosensing group. He, as part of Cambridge-M.I.T i-Teams, examines, identifies, and analyzes commercial potentials for an Intelligent Textbook technology, which uses an artificial intelligence engine, with real target customers in relevant industries. At present, GL is interested in pursuing a career that combines technology and analytical expertise, veiled in a business management environment. He is a member of Churchill College. GAJA received his B.Sc. degree in electrical/electronic engineering from Cardiff University, Wales, UK, in 1979 and his Ph.D. degree in electrical/electronic engineering from the University of Cambridge, Cambridge, UK, in 1983. He has held the 1966 Professorship in Engineering with the University of Cambridge since 1998. He currently heads the Electronics, Power and Energy Conversion Group, one of four major research groups within the Electrical Engineering Division of the Cambridge Engineering Faculty. He has worked for 25 years on integrated and discrete electronic devices for power conversion and on the science and technology of carbon-based electronics for 22 years. He has an active research program on the synthesis and electronic applications of carbon nanotubes and other nanoscale materials. He also has research interest in nanomagnetic materials for spin transport devices. He currently sits on the steering committee of the Nokia-Cambridge University Strategic Collaboration on Nanoscience and Nanotechnology and is the head of the Nokia-CU Nanotechnology for Energy Programme. His current research is focused on integrated power conversion circuits. He has previously held faculty positions at the University of Liverpool (Chair in Electrical Engineering), University of Cambridge, and University of Southampton. He has held the UK Royal Academy of Engineering Overseas Research Award at Stanford University, Stanford, CA, USA, and been a Royal Society visitor at the School of Physics, University of Sydney, Sydney, New South Wales, Australia. He has published over 450 journal and conference papers. GAJA was elected a Fellow of the Royal Academy of Engineering in 2004. In 2007, he was awarded the Royal Academy of Engineering Silver Medal ‘for outstanding personal contributions to British engineering.’

## Declarations

### Acknowledgments

MLPT thanks the Ministry of Higher Education Malaysia and the Universiti Teknologi Malaysia (UTM) for the award of advanced study fellowship leading to a Ph.D. degree at the University of Cambridge. This work is partially supported by a New Academic Staff (NAS) research grant (vot no.: R.J130000.7723.4P030) and the UTM Research University Grant (GUP) (vot no.: Q.J130000.2623.05J42). The authors also gratefully acknowledge the suggestions made by anonymous reviewers that have enhanced the quality of the manuscript greatly.

## Authors’ Affiliations

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