Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

Abstract

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (I_on/I_off), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Background

Carbon nanotubes (CNTs) have been proposed as an alternative channel material to silicon (Si), based on their quantum transport properties which, in principle, allow ballistic transport at room temperature. CNT ballistic modeling[1] has been used to assess the performance of the device at the HSPICE circuit level[2]. Device modeling is vital for projecting the practical performance of a CNT transistor as a switching device in integrated circuits (ICs).

We report the potential of a CNT channel through modeling as a substitute to a silicon channel in a scaled metal-oxide-semiconductor field-effect transistor (MOSFET) for logic applications. By scaling the Si transistor and the density of states (DOS) of the CNT, we observe good agreement between CNT and ballistic Si MOSFET[3] in the drain current–voltage (I V) output characteristics. Output current is critical in determining the switching speed of a transistor in logic gates. We show that the output performances of CNT and Si channel devices are similar in the 45-nm node experimental data. However, the modeling results point to significant reduction in drain-induced barrier lowering (DIBL) and related high field effects in the CNT compared to the short-channel nanoscale Si MOSFET at the same output current. We also assess the effect of channel area restructuring on electric field properties as well as the role of the DOS in determining CNT current. Unlike in the Si MOSFET, it is seen that the performance of a CNT channel is enhanced when the source/drain width is minimized rather than the channel length due to gate-to-source/drain parasitic fringe capacitances. MOSFET scaling according to Moore's law is limited by process controllability.

Methods

Carbon nanotube and MOSFET modeling

A layout of a carbon nanotube field-effect transistor (CNTFET) is shown in Figure1. The area of the channel is defined by the width (W) of the source and drain contacts and the length (L) of the nanotube. Details of the ballistic MOSFET modeling can be found in our previous work[3].

Figure 1

Top view of CNTFET device.

The analytical carbon nanotube model comes from the work of Rahman et al.[4, 5] where we have extended the universal DOS spectral function into a numerical calculation for CNT conduction subbands. We have modified the DOS subroutine[6] to account for multimode transport[7]. To improve precision and accuracy in the simulation, the parameters in Table1 for MOSFET and CNTFET which incorporate quasi-ballistic transport scattering are extracted from CADENCE[8] and Javey et al.[9], respectively. CNTFET analytical models have been validated and agree well with experimental data[9, 10] particularly in the saturation region depicted in Figure2.

Table 1 Source and drain capacitance for multiple substrate insulator thickness

Figure 2

Simulated CNT drain characteristic versus 80-nm experimental data. Simulated single-subband CNT drain characteristic (solid lines) versus 80-nm experimental data with high-potassium (K)-doped source and drain doping (filled diamond) at V_G = 0 to 1.0 V in 0.2-V steps. (Adapted from[9]).

If a CNT can achieve the same current as a MOSFET, an identical channel area (A_MOS = A_CNT) can be maintained by setting the width of the physical space occupied by the CNTFET to be W_CNT = A_MOS / L_CNT. When W = L for the MOSFET, the general channel area can be expressed as A = (kL)², where k is the scaling factor. As such, a CNT channel with length, 2kL should attain the same current with W = 0.5kL. Thus, if the physical width of the CNT channel is W ≤ 0.5kL, there will not be any area drawback in output current due to the longer L. In fact, the maximum electric field in CNT is halved, giving E_mCNT = E_mSi / 2, and is significantly reduced as the CNT channel grows longer. For a CNT with L = 60 nm compared to a Si MOSFET with L = 45 nm, the maximum electric field is E_m = 0.83 E_mSi.

Device modeling

The top view of CNTFET with the source and drain contacts is shown in Figure1. The filled black rectangle represents the contact enclosure with dimension extracted from a generic 45-nm MOSFET process design kit (PDK) where S = 20 nm, C = 60 nm, and W_C = L_C = 100 nm. Nine capacitances are introduced into the carbon-based macromodel as illustrated in Figure3. They are the gate oxide capacitance C_ox, quantum capacitance C_Q, source capacitance C_s, drain capacitance C_d, substrate capacitance C_sub, source-to-bulk capacitance C_sb, drain-to-bulk capacitance C_db, gate-to-source capacitance C_gs, and gate-to-drain capacitance C_gd. The size of the contact is crucial as it ultimately influences C_sb and C_db. They are given in Table1 and can be written as

$$C_{\text{sb}}\text{or}{C}_{\text{db}}={\epsilon }_{\text{ins}}\left(\frac{WL}{t_{\text{ins}}}\right)\text{,}$$

(1)

where t_ins is the thickness of the insulator, W is the width of the contact, L is the length of the contact, and ε_ins is the permittivity of the insulator. The substrate insulator capacitance C_sub for CNTFET is given by

$$C_{\text{sub}\_\text{CNTFET}}=\frac{2\pi {\epsilon }_{\mathrm{ins}}}{ln\left(\frac{4t_{\mathit{sub}}}{d}\right)}\text{,}$$

(2)

where t_sub is the substrate oxide thickness and d is the diameter of CNT. The intrinsic gate capacitance C_G of CNTFET is a series combination of gate oxide capacitance C_ox and quantum capacitance C_Q[11]. The C_ox of a CNTFET[12–14] is shown to be

$$\text{Nanotube}{C}_{\text{ox}}=\frac{2\pi {\epsilon }_{\text{ins}}}{ln\left(\frac{2t_{\text{ins}}+d}{d}\right)}$$

(3)

Figure 3

HSPICE macromodel for CNTFET.

The quantum capacitance is expressed by[15–17]

$$C_{\text{Q}}=\frac{2g_{\text{v}}{g}_{\text{s}}{q}^2}{h{v}_{\text{F}}}{\displaystyle \sum _i\frac{E}{\sqrt{E^2-{\left(E_{\text{Gi}}/2\right)}^2}}}\Theta \left(\left|E\right|-\frac{E_{\text{Gi}}}{2}\right)\text{,}$$

(4)

where g_s is the spin degeneracy, g_v is the valley degeneracy, E_Gi is the bandgap energy, and v_F is the Fermi velocity. The step function$\Theta \left(x\right)$ is equal to 1 when x > 0 and 0 when x < 0. The C_gs and C_gd are given as

$$C_{\text{gs}}=\frac{L_{\text{g}}{C}_{\text{ox}}}{2}\left[\frac{C_{\text{Q}}+C_{\text{s}}}{C_{\text{tot}}+C_{\text{Q}}}\right]\text{;}$$

(5)

$$C_{\text{gd}}=\frac{L_{\text{g}}}{2}{C}_{\text{ox}}\left[\frac{C_{\text{Q}}+C_{\text{d}}}{C_{\text{tot}}+C_{\text{Q}}}\right]\text{,}$$

(6)

where C_s and C_d are the source and drain capacitance fitting parameters, respectively,[1, 2] that are used to fit the experimental data and L_g is the length of the gate. The sum of C_gd and C_db gives the intrinsic capacitance C_int.

The square law is no longer valid for I-V formulation of short-channel MOSFET. Tan et al.[3] succinctly show the transformation of the square law that applies for the long channel to the linear law that is applicable for short-channel MOSFET. On the other hand, I-V formulation for the CNTFET model follows the quantum conductance principle that was developed by Rahman et al.[4, 5] and Datta[6]. The I-V model can be rewritten in terms of drain voltage V_d, source voltage V_s, and gate voltage V_G that is expressed by

$$I_{\text{ds}}\left(V_{\text{G}},V_{\text{d}},V_{\text{s}}\right)=G_{\text{ON}}\frac{k_{\text{B}}T}{q}\left[log\left(1+exp\left(q\left(E_{\text{F}}-V_{\text{sc}}\left(V_{\text{G}},V_{\text{d}},V_{\text{s}}\right)\right)/k_{\text{B}}T\right)\right)\right]-G_{\text{ON}}\frac{k_{\text{B}}T}{q}\left[log\left(1+exp\left(q\left(E_{\text{F}}-V_{\text{sc}}\left(V_{\text{G}},V_{\text{d}},V_{\text{s}}\right)-V_{\text{d}}-V_{\text{s}}\right)/k_{\text{B}}T\right)\right)\right]\text{,}$$

(7)

where G_ON is the ON-conductance, V_sc is also known as the channel surface potential[11], E_F is the Fermi energy, k_B is the Boltzmann constant, T is the temperature, and q is the electric charge. The equation is iteratively solved and hence includes the effect of gate voltage.

Model verification

In this section, the potential of CNT circuit design is assessed. Our simulation results in Figure4 indicate that CNTFET is able to provide drain current performance comparable to a 45-nm-gate length MOSFET. The model is successful in predicting expected output current levels in a sub-100-nm-channel CNT transistor experimental data. The DIBL effects and subthreshold swing (SS) are better suppressed in the CNT device, while the Si transistor demonstrates a moderate DIBL and SS due to short-channel effects as shown in Table2. Although the CNT has similar ON-current, it sustains I_on/I_off ratio of two orders of magnitude lower than Si MOSFET. The quantum ON-conductance limit of a ballistic single-walled carbon nanotube (SWCNT) and graphene nanoribbon with perfect contact is G_ON = 4e²/h and G_ON = 2e²/h (twice the fundamental quantum unit of conductance), respectively. Quantum capacitance C_Q is directly proportional to the density of states of the semiconductor but inversely proportional to the electrochemical potential energy. When C_Q becomes smaller than C_ox, a large quantity of the electrochemical potential energy is needed to occupy the states above the Fermi energy. This results in the reduction in overall intrinsic gate capacitance C_G and limits the channel charge in a semiconductor and ultimately the I-V characteristic of the FET devices. Comparison in Table2 shows that MOSFET has a higher cutoff frequency due to higher transconductance as compared to CNTFET with lower capacitances.

Figure 4

 I  -  V  characteristic of SWCNT model, semiconducting and metallic CNT experimental data. I V characteristic of a 50-nm SWCNT model (dotted lines) demonstrated in comparison to L ≈ 50 nm semiconducting CNT experimental data (filled diamond). Metallic CNT experimental data are also shown (filled circle). Inset shows 45-nm MOSFET characteristics where the dimension is given in Table2. Initial V_G at the top for CNT and MOSFET is 1 V with 0.1-V steps. (Adapted from[10]).

Table 2 Device model specification at  V  _GS  = 1 V

First, MOSFET logic circuits are built based on a 45-nm generic PDK. The MOSFET designs are then compared with carbon-based circuit models that consist of prototype digital gates implemented in HSPICE circuit simulator. These CNTFETs use 45-nm process design rules, namely the minimum contact size. For a fair assessment, both MOSFET and CNTFET are designed to provide similar current strength (≈46 to 50 μA).

An appropriate CNTFET device was fabricated to investigate the contact resistance. SWCNTs were grown in situ using the bimetal catalyst iron-molybdenum (Fe-Mo)[11] on a silicon-on-insulator substrate with 200 nm of thermally grown SiO₂. Metal contacts were patterned by electron beam lithography, and 60 nm of palladium (Pd) contacts was deposited to form a back gate geometry transistor. The spacing between the Pd contacts varied between 56.6 nm and 1.06 μm as shown in Figure5.

Figure 5

Scanning electron microscope image of Pd contacts over the nanotube with each contact being labeled. Black arrows are used to point to the SWCNT.

A four-probe measurement was carried out at room temperature to extract the resistance characteristics of the carbon nanotube that was used to form the transistor channel. The normalized resistances were 0.495, 0.744, 0.118, and 0.450 MΩ/nm for R_2,3, R_2,4, R_3,4, and R_4,5, respectively, where indices indicate Pd contact labels. The diameter of the SWCNT is 1.5 nm. Calculation shows that the 415-nm nanotube resistance is 27.8 kΩ that is almost equal to the theoretical R_ON = h/q² = 25.812 kΩ and four times larger than the theoretically lowest quantum resistance of the SWCNT, R_ON = h/4q² = 6.5 kΩ.

Though at 415-nm channel length ballistic transport is not preserved in the CNT, it is still only factor 4 larger than the theoretically expected minimum, suggesting that scattering is not extensive. Nevertheless, the model which assumes ballistic transport predicts similar saturation current levels (≈50 μA) for both the 50- and 415-nm channel devices, as illustrated in Figure5. Practically, this suggests that one must have CNT channel lengths below approximately 100 nm or even low contact resistance in order to utilize ballistic transport in them.

Results and discussion

Circuit analysis

CNT circuit logic operation is simulated in HSPICE based on the compact models described in the ‘Model verification’ section. Figures 6,7,8,9, and10 show the schematic of NOT, NAND2, NOR2, NAND3, and NOR3 gates and their corresponding input and output waveform, respectively. It is shown that CNTFETs are able to provide correct logical operation as MOSFET from the output waveform. In this simulation, it is assumed that both the n-type and p-type CNTFETs have symmetrical I-V characteristics. The performance evaluation of these Boolean operations is listed in Table3.

Figure 6

Schematic of NOT gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).

Figure 7

Schematic of two-input NAND2 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).

Figure 8

Schematic of two-input NOR2 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).

Figure 9

Schematic of three-input NAND3 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).

Figure 10

Schematic of three-input NOR3 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).

Table 3 45-nm process propagation delay computation between CNTFET (with and without interconnect) and MOSFET (post-layout simulation)

Performance evaluation

The unity current gain cutoff frequency for the CNTFET circuit model is depicted in Figure11. The model uses a copper interconnect of 45 nm with a 100-nm and 500-nm substrate insulator thickness. The interconnect length varies from 0.01 to 100 μm. The length of interconnects affects considerably the frequency response. The lower length interconnect enhances the cutoff frequency. The substrate thickness also plays an active role in lower length domain. No distinction with the substrate thickness is visible beyond 1-μm interconnect length. The figure of merit for logic devices, namely power-delay product (PDP) and energy-delay product (EDP) metrics, are given as

$$\text{PDP}=P_{\text{av}}\times t_{\text{p}}\text{;}$$

(8)

$$\text{EDP}=\text{PDP}\times t_{\text{p}}\text{,}$$

(9)

where P_av is the average power and t_p is the propagation delay.

Figure 11

Cutoff frequency for CNTFET. Cutoff frequency for CNTFET with interconnect length from 0.01 to 100 μm with a source and drain contact area equivalent to that of a 45-nm MOSFET and substrate insulator thickness of 100-nm and 500-nm.

Figure12 shows the PDP of CNTFET and MOSFET logic gates for the 45-nm process. The simulation results show that the PDP of CNTFET-based gates are lower than that of MOSFET-based gates by several orders of magnitude[18]. For the 45-nm process, the PDP of CNTFET-based gates is two times smaller than that of MOSFET-based gates with L_wire = 5 μm. It increases to 1,000 times without interconnect (L_wire = 0 μm).

Figure 12

PDP of CNTFET versus MOSFET.

Figure13 shows the EDP of CNTFET and MOSFET logic gates for the 45-nm process. EDP for CNTFET-based gates with 5 μm is comparable to MOSFET. As a result, the wire length should be kept shorter than 5 μm in order to obtain energy-efficient low-power architecture.

Figure 13

EDP of CNTFET versus MOSFET.

Figures 14 and15 show 3D plots of PDP and EDP for CNTFET with copper interconnect up to 5 μm in length. We observe a 28% improvement of PDP while EDP reduces by 39% for NAND3 that adopts the 45-nm process compared to the one that uses the 90-nm process contact size.

Figure 14

3D plot of PDP of CNTFET logic gates. The copper interconnect length is up to 5 μm for t_node = 45 nm and t_sub = 500 nm.

Figure 15

3D plot of EDP of CNTFET logic gates. The copper interconnect length up to 5 μm for t_node = 45 nm and t_sub = 500 nm.

Table3 shows the average propagation delay, t_p, for logic gates NOT, NAND2, NAND3, NOR2, and NOR3 for CNTFET with and without interconnect in comparison with MOSFET during post-layout simulation. It is found that NAND3 or NOR3 has the largest propagation delay since both of them has multiple fan-in and fan-out each. In the digital logic simulation of CNTFET, we use an average length of 5 μm per fan-out.

Conclusions

We have established that a longer channel CNT is capable of delivering output currents comparable to those from a 45-nm-node Si MOSFET. This is possible due to the preservation of ballistic transport over distances approaching 100 nm and the higher current density of a single CNT forming the channel. Consequently, in the same practical channel area, a CNT allows reduction of short-channel effects as it has a lower E_max, leading to a lower DIBL and off current.

Devices with thicker substrate insulator and smaller source drain contact area give the highest frequency. In addition to that, logic gates NOT, NAND2, NAND3, NOR2, and NOR3 and their corresponding input and output waveforms are given. The interconnect length of cascading logic gates has a profound effect on the signal propagation delay. In the digital logic simulation, the key limiting factor for high-speed CNT-based chips is the interconnect itself. The performance enhancement of these carbon-based material is negligible if the interconnect capacitance is not reduced significantly with transistor feature size. Bundled metallic MWCNTs are seen as a potential candidate to replace copper interconnects as future IC interconnects once the challenges of integrating CNT interconnects onto existing manufacturing processes are met.

We also show that ballistic transport is not maintained in a CNT when contact resistance is large. A good fit to the data output characteristics from a 50-nm CNT channel device is obtained. As mean free path in a CNT is very long, often exceeding 1 μm, the ballistic process plays a predominant role, similar to one discussed extensively by Riyadi and Arora[19]. In fact, they define a new feature, named ballisticity. The truly ballistic transport is possible as channel length approaches zero. In a finite length, there are always finite probabilities of scattering.

Authors’ informations

MLPT was born in Bukit Mertajam, Penang, Malaysia, in 1981. He received his B. Eng. (electrical-telecommunication) and M. Eng. (electrical) degrees from Universiti Teknologi Malaysia (UTM), Skudai, Malaysia, in 2003 and 2006, respectively. He conducted his postgraduate research in nanoscale MOSFET modeling at the Intel Penang Design Center, Penang, Malaysia. He recently obtained his Ph.D. degree in 2011 at the University of Cambridge, Cambridge, UK. He is a senior lecturer at UTM. His present research interests are in device modeling and circuit simulation of carbon nanotube, graphene nanoribbon, and MOSFET. MLPT is an IEEE member, member of IET (MIET), graduate member of IEM (GRAD IEM), and member of Queens' College. GL was born in Chania, Crete, Greece in 1983. He holds a B. Eng. (computing and robotic systems) degree from the Department of Electric Engineering in Liverpool University and a Ph.D. degree in engineering from the University of Cambridge. His Ph.D. thesis was in the area of fabricating and characterizing single-walled carbon nanotubes and ZnO nanowire transistors and sensors. He has also worked as a researcher at Nokia's Eurolab between 2009 and 2011 and particularly in developing novel sensors as part of Nokia's Nanosensing group. He, as part of Cambridge-M.I.T i-Teams, examines, identifies, and analyzes commercial potentials for an Intelligent Textbook technology, which uses an artificial intelligence engine, with real target customers in relevant industries. At present, GL is interested in pursuing a career that combines technology and analytical expertise, veiled in a business management environment. He is a member of Churchill College. GAJA received his B.Sc. degree in electrical/electronic engineering from Cardiff University, Wales, UK, in 1979 and his Ph.D. degree in electrical/electronic engineering from the University of Cambridge, Cambridge, UK, in 1983. He has held the 1966 Professorship in Engineering with the University of Cambridge since 1998. He currently heads the Electronics, Power and Energy Conversion Group, one of four major research groups within the Electrical Engineering Division of the Cambridge Engineering Faculty. He has worked for 25 years on integrated and discrete electronic devices for power conversion and on the science and technology of carbon-based electronics for 22 years. He has an active research program on the synthesis and electronic applications of carbon nanotubes and other nanoscale materials. He also has research interest in nanomagnetic materials for spin transport devices. He currently sits on the steering committee of the Nokia-Cambridge University Strategic Collaboration on Nanoscience and Nanotechnology and is the head of the Nokia-CU Nanotechnology for Energy Programme. His current research is focused on integrated power conversion circuits. He has previously held faculty positions at the University of Liverpool (Chair in Electrical Engineering), University of Cambridge, and University of Southampton. He has held the UK Royal Academy of Engineering Overseas Research Award at Stanford University, Stanford, CA, USA, and been a Royal Society visitor at the School of Physics, University of Sydney, Sydney, New South Wales, Australia. He has published over 450 journal and conference papers. GAJA was elected a Fellow of the Royal Academy of Engineering in 2004. In 2007, he was awarded the Royal Academy of Engineering Silver Medal ‘for outstanding personal contributions to British engineering.’