- Nano Express
- Open Access
Interface traps and quantum size effects on the retention time in nanoscale memory devices
© Mao; licensee Springer. 2013
- Received: 31 July 2013
- Accepted: 23 August 2013
- Published: 29 August 2013
Based on the analysis of Poisson equation, an analytical surface potential model including interface charge density for nanocrystalline (NC) germanium (Ge) memory devices with p-type silicon substrate has been proposed. Thus, the effects of Pb defects at Si(110)/SiO2, Si(111)/SiO2, and Si(100)/SiO2 interfaces on the retention time have been calculated after quantum size effects have been considered. The results show that the interface trap density has a large effect on the electric field across the tunneling oxide layer and leakage current. This letter demonstrates that the retention time firstly increases with the decrease in diameter of NC Ge and then rapidly decreases with the diameter when it is a few nanometers. This implies that the interface defects, its energy distribution, and the NC size should be seriously considered in the aim to improve the retention time from different technological processes. The experimental data reported in the literature support the theoretical expectation.
- Interface trap
- Quantum-size effect
- Retention time
The performance and reliability of metal-oxide semiconductor is significantly influenced by the quality of the grown Si/SiO2 interface. The interface trap as a function of energy in the Si band gap exhibits two peaks, 0.25 and 0.85 eV for Si(110)/SiO2 interface  and 0.31 and 0.84 eV for Si(111)/SiO2 interface . The Pb center resides on flat surfaces (terraces), not at ledges ; it is considered as the main source of defects at the Si(111)/SiO2 interface. It was named as Pb0 with reference to the Pb1 center on Si(100). The interface defect is amphoteric that is a donor level below mid gap and an acceptor level above mid gap. Memory structures based on nanocrystalline (NC) semiconductor have received much attention for next-generation nonvolatile memory devices due to their extended scalability and improved memory performance [4–6]. Recently, the quantum size effects caused by the channel material NC Si neglecting the interface charge on the threshold voltage of thin-film transistors without float gate  and on charging the dynamics of NC memory devices  have been studied. Here, both the quantum size effects caused by the float gate material NC and the interface traps effects on the retention time of memory devices are studied.
The Fermi-Dirac distribution function F(E) for donor interface traps is (1 + 2 exp[(E F − E)/(kT)])−1 and that for the acceptor interface traps is (1 + 4 exp[(E − E F )/(kT)])−1.
where ϵb is dielectric constant of bulk Ge. The characteristic radius for Ge is 3.5 nm. Considering the fill factor, the average dielectric constant of NC Ge layer can be estimated using parallel capacitor treatment.
The top of the valence band of p-type silicon bends upward (ψs < 0 and Εs < 0) which causes an accumulation of majority carriers (holes) near the interface. Thus, the interface traps capture more holes when the float gate has been charged with electrons . It results that the electric field across the tunneling oxide layer increases according to Equation 5, the transmission coefficient through the tunneling oxide layer increases, and the retention time decreases. Whereas, the top of the valence band of n-type silicon bends upward which causes a depletion of majority carriers (electrons) near the interface, and the interface traps capture less holes or capture electrons if the band bends even more so that the Fermi is level below mid gap . Thus, it results that the electric field across the tunneling oxide layer decreases, the transmission coefficient decreases, and the retention time increases. Additionally, such a method is still valid for metal (or other semiconductor) NC memory in just using their equations to substitute Equations 9, 10, and 11 for NC Ge.
In Equation 13, S l = ml + 1k l /m l kl + 1, and the effective masses and momenta were discretized as m l = m*[(xl − 1 + x l )/2] and k l = k[(xl − 1 + x l )/2], respectively, xl being the position of l th boundary. The Fermi-Dirac distribution was used in the tunneling current calculations, and the maximum of the longitudinal electron energy was set at 20 kBT above the conduction band.
The effective electron mass 0.5 m0 of SiO2, 0.26 m0 of silicon, 0.12 m0 of NC Ge  and the relative dielectric constant of the SiO2, Si, and Ge of 3.9, 11.9, and 16, respectively, have been used in calculations . The published electron affinities of crystalline silicon, SiO2, and Ge are 4.05, 0.9, and 4.0 eV, respectively . The thickness of the tunneling oxide layer and control oxide layer are 4 and 25 nm, respectively. NA is 1 × 1015 cm−3, the temperature is 300 K, and the silicon substrate and gate are grounded in the following calculations.
The results for Si(100) can be easily explained because of the larger leakage current difference from those for Si(111) and Si(110). The leakage current exponentially increases due to a large increase in the Ec according to Equation 9 that leads to the leakage current exponentially increase. It implies that the ratio of the effects of interface charge on the leakage current to that of the Ec becomes smaller, and thus, the difference between those for different silicon orientations become smaller with the decrease in the diameter of NC. Whatever they have is the same trend for the different diameters.
In conclusion, the effects of Pb defects at Si(100)/SiO2 interface for different silicon orientations on the discharging dynamics of NC Ge memory devices have been theoretically investigated. The results demonstrate that the Si(100)/SiO2 interface have the best discharge dynamics, and Si(110)/SiO2 and Si(111)/SiO2 interface are nearly same. It is also found that the retention time firstly increases, then decreases with the decrease in the diameter of NC when it is a few nanometers. The results also demonstrate that the effects of the interface traps on the discharge dynamics of NC Ge memory devices should be seriously taken into account. The experimental data reported in the literature [14, 15] support the theoretical expectation.
Ling-Feng Mao received the Ph.D degree in Microelectronics and Solid State Electronics from the Peking University, Beijing, People's Republic of China, in 2001. He is a professor in Soochow University. His research activities include modeling and characterization of quantum effects in MOSFETs, semiconductors and quantum devices and the fabrication and modeling of integrated optic devices.
The author acknowledges financial support from the National Natural Science Foundation of China under Grant 61076102 and Natural Science Foundation of Jiangsu Province under Grant BK2012614.
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