Figure 6From: Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowiresWire faceting. (a , b , c , d , e) STM images showing the morphology of the wires. The bottom insets of (c) show, respectively, (left panel) the line profile and (right panel) the FP of the wire in (c).Back to article page