Influence of post-annealing on the off current of MoS2 field-effect transistors
© Namgung et al.; licensee Springer. 2015
Received: 6 October 2014
Accepted: 20 January 2015
Published: 11 February 2015
Two-dimensional materials have recently been spotlighted, due to their unique properties in comparison with conventional bulk and thin-film materials. Among those materials, MoS2 is one of the promising candidates for the active layer of electronic devices because it shows high electron mobility and pristine band gap. In this paper, we focus on the evolution of the electrical property of the MoS2 field-effect transistor (FET) as a function of post-annealing temperature. The results indicate that the off current drastically decreased at 200°C and increased at 400°C while other factors, such as the mobility and threshold voltage, show little variation. We consider that the decreasing off current comes from the rearrangement of the MoS2 film and the elimination of the surface residue. Then, the increasing off current was caused by the change of the material's composition and adsorption of H2O and O2.
KeywordsMolybdenum disulfide MoS2 Field-effect transistors On/off current ratio Field-effect mobility
Two-dimensional (2D) materials, such as graphene and transition metal dichalcogenides (MoS2, MoSe2, WS2, etc.), are widely used recently for fabricating next-generation nanoelectronics [1-10]. This is because of the high electron mobility of 2D materials, compared with the original bulk material. Typically, graphene shows over 5,000 cm2/Vs of electron mobility , and this feature is valuable for applications such as sensors  and photovoltaic cells . However, graphene has a fundamental disadvantage for electronic devices, which is the lack of an intrinsic band gap. This has resulted in several reports of insufficient on/off current ratio of field-effect transistors (FETs) [14-17].
Though engineering a band gap of graphene can be an answer for this technical issue, it increases the number of fabrication steps [18,19] and reduces the electron mobility of graphene . As an alternative, MoS2 has an intrinsic band gap, which leads to reduced off current. For example, MoS2 FETs have in general recorded an on/off current ratio of 105 ~ 1010 [21-28], and some MoS2 FETs with high-k dielectrics have recorded an electron mobility of 200 cm2/Vs, which is higher than that of band gap-engineered graphene .
Many reports have announced that the annealing process is dispensable for improving the electrical property of various FETs using original IV semiconductors , oxide semiconductors [30,31], layered semiconductors [32-34], etc. In the case of 4H-SiC included in the original IV, the annealing process created a passivation layer at the interface, and device parameters were improved, such as the electron mobility and subthreshold swing (SS). In the case of InGaZnO included in oxide semiconductors, the annealing process rearranged defects, and all the device parameters improved, such as V th, SS, mobility, hysteresis, and the on/off current ratio. For graphene included in a layered material, the annealing process eliminated the resist residue on the surface and increased conductance.
For MoS2, a few results have been reported from the viewpoint of the post-annealing process [21,23,26]. One paper showed variation in the optical property, by observing the change of the photoluminescence (PL) peak of single-layer MoS2 with respect to post-annealing . Although it did not evaluate the electrical property of FETs, it reported that the annealing process induced structural rearrangement, and this could also affect the electrical properties of MoS2. Another paper investigated the influence of vacuum annealing on MoS2 FET during measurement of the electrical property . It announced a drastic improvement of electrical performance by annealing, especially in the conductance of the device. However, it focused on the electrical characteristics caused by movement of carriers at elevated temperature, which consequently present the thermally activated characteristics of MoS2 FET. Here, we summarize the evolution of the electrical performance of MoS2 FET at room temperature, which is the conventional operating temperature, with various post-annealing temperatures.
MoS2 flakes were prepared using a scotch-tape micromechanical cleavage technique, from bulk MoS2 crystal (429ML-AB, SPI Supplies, Inc., West Chester, PA, USA), and were transferred to highly doped silicon substrates covered with 300-nm-thick SiO2. Source and drain (S/D) were patterned by photolithography, and 50-nm-thick Ti was deposited by an e-beam evaporator. Then, a conventional lift-off process was accomplished for the patterning of the S/D electrode. The fabricated MoS2 FET was annealed in a nitrogen environment for 2 h at various temperatures. The electrical characteristic was measured under atmospheric pressure at room temperature. Furthermore, the thicknesses of the MoS2 flakes were measured using atomic force microscopy (AFM; XE-100, Park Systems, Suwon, South Korea).
Results and discussion
Device performance summary
On/off current ratio
On current (A)
Off current (A)
Field-effect mobility (cm 2 /Vs)
Subthreshold swing [V/dec]
3.5 × 1001
6.38 × 10−04
1.80 × 10−05
1.7 × 1007
4.06 × 10−04
2.34 × 10−11
8.7 × 1006
3.87 × 10−04
4.43 × 10−11
3.2 × 1000
8.39 × 10−05
2.66 × 10−05
Under those trends, the status of the device can be categorized into two regions. The first region, here termed region I, is that in which the device performance improves from room temperature to 200°C with decreasing off current and increasing field-effect mobility. The second region (region II) is that in which the device performance degrades from 200°C to 400°C with increasing off current and decreasing field-effect mobility.
In region I, the decrease of off current is thought to be caused by the atomic arrangement of MoS2 atoms in local sites due to thermal energy. This kind of internal structural modification ends up with the release of a native point defect at the interface between the insulator and the channel material . The interface properties between the MoS2 and SiO2 seemed to be improved, in that the subthreshold swing decreased from 36.20 to 0.91 [V/dec], as the post-annealing temperature increased to 200°C.
Also, it is thought that the resist residue included during the fabrication process might be eliminated by the post-annealing process. The photoresist and organic materials from the 3M tape (3M, St. Paul, MN, USA) are one of the plausible candidates to be eliminated, and specifically, elimination of the photoresist residue of the graphene FET was observed with improvement of the device performance during the post-annealing process .
In region II, as mentioned, an increase of the off current by 5 or 6 orders was measured.
MoS 2 composition ratio change based on XPS data
Simplified ratio (let Mo be 1)
From a different point of view, adsorption of H2O and O2 on MoS2 can also be one of the reasons for the increase of the off current. Under vacuum conditions, the off current actually decreased by average 102 level and this change is elaborated in Additional file 1: Figure S3. Therefore, it is guessed that adsorption was carried out after the high-temperature annealing process for the measurement of electrical characteristics at an atmosphere environment, and it was also supported by the case of graphene .
The evolution of off current for MoS2 FET due to annealing temperature was systematically analyzed. As a result, the off current decreased up to 200°C annealing and increased for higher temperature annealing. Plausible explanations for the decrease in off current are the rearrangement of MoS2 atoms and the elimination of the surface residue. Possible explanations for the increase in off current are the changes of the material's composition ratio and adsorption of H2O and O2. This research is meaningful in that the off current was controlled by the post-annealing temperature.
This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ‘IT Consilience Creative Program’ (NIPA-2014-H0201-14-1002) supervised by the NIPA (National IT Industry Promotion Agency).
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