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Figure 6 | Nanoscale Research Letters

Figure 6

From: Conductive-bridging random access memory: challenges and opportunity for 3D architecture

Figure 6

I-V hysteresis for a Cu/Ge0.3Se0.7/W memory device and typical P/E cycles of a Cu/Ge0.2Se0.8/W memory device. (a) I-V hysteresis of more than 100 consecutive DC cycles for a Cu/Ge0.3Se0.7/W memory device. The size of the memory device is 4 × 4 μm2. (b) Typical P/E cycles of a Cu/Ge0.2Se0.8/W memory device. Every P/E cycle was recorded. This suggests that the P/E cycles are more than 105.

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