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Fig. 2 | Nanoscale Research Letters

Fig. 2

From: A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step

Fig. 2

a Cross-sectional schematic of the heterostructured SiO2/Ge QD/SiO2/SiGe n-MOSFET. The gate-stacking region also represents the structural core of the heterostructured MOS capacitor. b Frequency-dependent C-V characteristics of the heterostructured MOS capacitors, where C/C ox represents the normalized capacitance. The inset in b shows the corresponding I-V behavior. c D it values extracted from high-/low-frequency C-V curves in the temperature range of 300–77 K

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