Fig. 5From: A multi-subband Monte Carlo study on dominance of scattering mechanisms over carrier transport in sub-10-nm Si nanowire FETsCarrier density and ratio of surface carrier population to the total one. a The line density of hole carriers that is plotted as a function of gate biases for a 3 nm × 3 nm and a 8 nm × 8 nm cross-section. A negatively increasing gate voltage not only fills more carriers but generally creates stronger band bending in channels, increasing the chance for carriers to experience the corner effect. b The ratio of surface carrier (staying within 1.0 nm from channel surfaces) population to the total one that is plotted as a function of line densities of carriers for a 3 nm × 3 nm and a 8 nm × 8 nm cross-section. Although the corner effect may not be remarkable in narrower channels where cross-sections are not large enough to have clear band bending, the chance for the surface roughness scattering would be still high since more carriers are then placed near channel surfacesBack to article page