- Nano Express
- Open Access
Inexpensive transparent nanoelectrode for crystalline silicon solar cells
© The Author(s). 2016
Received: 20 March 2016
Accepted: 22 June 2016
Published: 29 June 2016
We report an easily manufacturable and inexpensive transparent conductive electrode for crystalline silicon (c-Si) solar cells. It is based on a silver nanoparticle network self-forming in the valleys between the pyramids of a textured solar cell surface, transformed into a nanowire network by sintering, and subsequently “buried” under the silicon surface by a metal-assisted chemical etching. We have successfully incorporated these steps into the conventional c-Si solar cell manufacturing process, from which we have eliminated the expensive screen printing and firing steps, typically used to make the macro-electrode of conducting silver fingers. The resulting, preliminary solar cell achieved power conversion efficiency only 14 % less than the conventionally processed c-Si control cell. We expect that a cell with an optimized processing will achieve at least efficiency of the conventional commercial cell, but at significantly reduced manufacturing cost.
Transparent conductive electrodes (TCE) are important components of photovoltaic and photonic devices, such as displays, light sources, detectors, and solar cells [1–6]. Most common TCE used today are based on doped metal oxides, such as indium tin oxide (ITO) [7, 8]. However, the relatively high cost, limited optoelectronic performance, and mechanical brittleness exclude these from many applications, such as in flexible displays [9, 10]. Recently, research progress in nanomaterials has opened new directions for alternative TCE: based on carbon nanotubes (CNT) [11, 12], graphene [13, 14], metal nanowires [15, 16], and metal grids [17, 18]. As an example, metal nanowires have been shown to combine the optoelectronic advantages with the low-cost manufacturing, including the high-through put roll-to-roll processing [10, 19]. In planar configurations, and on transparent, low dielectric constant substrates, their optical  and/or photovoltaic  performance has been comparable, or better than that of the commonly used ITO. Importance of the dielectric environment in controlling optical response of metallic nanoarrays has been also demonstrated .
One of the most important areas where development of novel TCE has been critical is the solar photovoltaics (PV). Currently, while an excellent suppression of the reflection is achieved in crystalline silicon (c-Si) solar cells by the chemical surface texturing combined with the anti-reflection coating (ARC), a moderate conductivity of the overdoped underlying silicon requires a dense network of macroscopic metallic connecting bars/fingers [22, 23]. These, in turn, shadow the active surface of the cell, compromising the efficiency. To address this issue, in our previous work, we have developed a TCE based on metallic nanowires assembled directly in the micro valleys of a textured c-Si surface, like that employed in crystalline solar cells . These nanowires were formed from silver nanoparticles deposited directly on the surface, and subsequently transformed into wires by microwave or furnace sintering. This nanoparticle nanonetwork (NNN) achieved an impressive optoelectronic performance, with reflectance of ~16 % without ARC and <5 % with ARC, as well as a good in-plane electrical conductivity of ~15 ohms/sq . A logical next step has been since to test this new TCE on a functional solar cell, by replacing the conventional screen-printed TCE. Here, we provide such a demonstration, made possible by an addition of a critically important step in the NNN processing: a “burial” of the assembled NNN under the silicon surface by metal-assisted chemical etching [25, 26]. The resulting buried NNN (BNNN) not only significantly improves the contact of the network to the silicon but also reduces the TCE reflectance, due to the hidden/cloaked nature of the buried network. We have successfully incorporated these steps of BNNN processing into the conventional c-Si solar cell manufacturing process, just after the junction formation and before the nitride deposition and processing. All the other processes remained unchanged, except that the expensive screen-printed TCE processing and firing steps have been eliminated. The resulting solar cell, not yet optimized, achieved power conversion efficiency only 14 % less than the conventionally processed c-Si control cell, but its manufacturing cost has been significantly reduced.
Silver ink synthesis
The starting point in making BNNN TCE is the nanoparticle ink. The silver ink is produced by a typical wet-chemical method [27, 28], resulting in NP diameter of 100–200 nm. Making the ink involves reducing silver nitride (0.1 M) (99 %, Sigma-Aldrich) in an ethylene glycol solution in the presence of polyvinylpyrrolidone (PVP) (0.6 M) (MW ≈ 40000, Sigma-Aldrich) at 170 °C and stirring at 2000 rpm for 30 min. The ethylene glycol is both a reducer and a solvent, and PVP is a surfactant. This procedure is subsequently followed by centrifuging, rinsing, and re-dispersing the silver nanoparticles in methanol or ethanol.
Wafer texturing and p-n junction fabrication
In this work, we incorporate the BNNN processing into the standard c-Si solar cell fabrication. We begin this fabrication with silicon substrate texturing. A silicon Si (100) wafer (p-type, 1 Ω·cm resistance, 15.6 × 15.6 cm2) was textured in a standard alkali solution, and then before the PECVD doping to form the p-n junction, its native oxide was etched away in a 0.5 % diluted HF. The texturing resulted in micro-pyramid formation (typically ~1.5 μm tall and ~3 μm wide at base). PCl3 gas was used in the PECVD chamber as the n-doping source and the junction formed at the depth of ~300 nm. The processed wafer was subsequently washed in 1 % diluted HF solution to remove the phosphorous silicate glass (PSG), the unwanted by-product of the doping process. This was followed by the immersion of the wafer in de-ionized water for 10 min to remove the residual HF.
Nanoparticle deposition and sintering
In the next step, the silver nanoparticle ink was spray-deposited on the surface of the textured and doped wafer. Within a few minutes, the capillary forces cause the nanoparticles to agglomerate in the deep valleys in between the texture pyramids. This process is enhanced with mechanical shaking of the wafer. At sufficient density, NP form continuous chains. However, a simple touching is not sufficient to assure good inter-particle contact, since NPs are coated with PVP insulating shells (by-product of their synthesis). To remove these, and to form continuous metallic wires by pre-melting, we implemented anneal/sintering in a microwave oven and in a furnace. The microwave sintering [29, 30] was done in a commercial microwave oven operating at 2.46 GHz, with the output power of 80 W. A typical exposure time used was ~10 s to selectively heat and sinter the silver nanoparticles into a continuous conducting nanowire network. The furnace sintering was done in a commercial rapid thermal processor (RTP) (RTP-500, Beijing Eaststar Labs) at temperature of 320 °C and duration of 10 s. The sintering resulted in the formation of well-conducting NNN.
Metal-assisted chemical etching
In the next step, we employed the metal-assisted chemical etching (MacEtch method [25, 26]) to “bury” the NNN under the silicon surface. The textured Si sample with NNN was immersed into an ethanol-based etchant composed of 4.6 M HF and 0.1 M H2O2. The chemical or electrochemical reactions occur preferentially near the noble metal NP in an etchant consisting of HF and H2O2. The possible cathode and anode reactions are as follows [25, 26]: H2O2 + 2H+ → 2H2O + 2 h+ at the metal (cathode reaction), and at the anode, the Si substrate is directly oxidized and dissolved in a tetravalent state as follows Si + 4 h++4HF → SiF4 + 4H+ and SiF4 + 2HF → H2SiF6. With the Si oxidized and dissolved at the Si/metal interface by HF, the NNN sinks down (becomes “buried”) into the silicon substrate. Simultaneously, NNN scale-sized pits form on the silicon surface (as shown in Fig. 1f). The pit depth increases gradually with the duration of etching. To minimize the energy consumption, and to make the process more compatible with a large scale manufacturing, we chose the processing temperature to be ~25 °C (room temperature). The etching lasted from 1 to 60 s. Then, the sample was washed in distilled water several times to remove etching solution, followed by etching in 5 % HF for 2 min to remove the silicon oxide layer. This was followed by a repeated washing in distilled water and finally drying at 150 °C for 2 min. This processing resulted in BNNN. The etching time rates can be varied with the concentration of etchant.
In the next standard c-Si processing step, the hydrogen-doped SiN was thermally deposited and processed. This high-quality dielectric film serves double function. Firstly, it forms an ARC, which reduces the light reflection, and secondly, the hydrogen released from SiN during the heat processing passivates the silicon-nitride interface imperfections and thus increases dramatically the carrier lifetime. In our structure, modified by the presence of BNNN, the curing process occurs around the BNNN. This is different than in the standard process, where no metal is present at the silicon-nitride interface until the silver paste micro-particles deposited on the nitride are subsequently thermally forced (“fired”) to diffuse through the nitride. Both these processes (silver paste screen printing and “firing”) have been eliminated in our processing.
A continuous square Al film is used as a back contact deposited by thermal evaporation method. A crossed Ag strips (2 mm × 1.5 cm) is used as the front contacts to the BNNN on the front also by thermal evaporation. Before Ag strips deposition, the underneath SiN layer is etching away with protection of a crossed hollow mask.
The morphologies of samples were characterized by a commercial SEM system (JEOL JCM-5700, Tokyo, Japan). We used an X-ray diffraction system (PANanalytical, X`Pert-Pro MPD PW 3040/60 XRD with Cu-Kα1 radiation, the Netherlands) to do material analysis. The dark and illuminated I-V measurements of the solar cells were done with the solar simulator (Oriel Newport, USA). Both evaporations were done in thermal vacuum evaporations system (SKY Vacuum Technology Company, China). The reflectance was measured by employing the fiber optic spectrometer (Ocean Optics, USB 4000) and the integration sphere (Ocean Optics, FOIS-1). Silver NP area coverage was calculated by analyzing the SEM images via Photoshop CS5 software.
Results and discussion
The initial, fast decrease of R s (shown in Fig. 4b) and the slight shift of the dark I-V characteristics of the BNNN cell towards lower voltages, as compared with that for a conventionally processed cell, indicate a large carrier recombination. This is an expected result of the commercial cell surface texturing. This recombination rate can be dramatically reduced by a passivation treatment with SiN [32, 33].
Performance of the BNNN solar cells
Efficiency reduction factors for BNNN cells
Solar cell type
Efficiency reduction factor r = η/η control
c-Si BNNN (S2)
c-Si BNNN (S1)
Lower efficiency of the BNNN cells is primarily due to lower current density, which is clearly due to the higher reflectance of these cells, shown in Fig. 5. Note, that the sample “tSi + BNNN”, reflectance of which is shown in Fig. 3b, is different from samples S1 and S2 (Fig.5b). The sample “tSi + BNNN” is obtained with etching time of 10 s, not optimal for minimal R s, but samples S1 and S2 were obtained with etching time of 8 s, optimal for R s.
As discussed above, there is a rather narrow window where the etching time t e yields BNNN which is both very conductive and weakly reflecting. In the electro-optical performance tests, this time was t e = 8 s, but in the samples for the solar cell tests, which went through additional step of SiN processing, was most likely different. According to Fig. 4b, this dramatically changes the electro-optical performance. We expect that with better understanding and control of the BNNN processing, cell efficiencies can be increased to those of the conventionally processed cells, or possibly higher, keeping in mind the excellent result shown in Fig. 3b.
We stress that our BNNN solar cells are fabricated using a solution-processed method, less expensive than the standard production line process. We have estimated the cost of the full size BNNN solar cell to be ~$0.4, with ~$0.17 cost of nanoparticles and the rest the standard commercial processing costs, minus the screen printing and firing expenses. Cost of the conventionally processed solar cell (same size), including the screen printing and firing expenses is ~$0.5. Thus, the BNNN solar cell processing costs are about 80 % of those of the conventionally processed cell, a potential dramatic advantage once the BNNN process is perfected to be used on full wafers, and with the BNNN cell efficiencies at least that of the conventional (commercial) solar cells.
In conclusion, we have demonstrated a novel, highly transparent and conducting electrode (BNNN), which provides a high-quality, ohmic contact to a textured crystalline silicon substrate. We demonstrate also preliminary results on the c-Si solar cells with BNNN, obtained by replacing the usual commercial screen-printed macro-electrode with our BNNN. The efficiency of our BNNN cell is only 14 % lower than that for the conventional/commercial control, while the manufacturing cost is only ~80 % of the commercial, because it avoids the two most expensive steps of the conventional processing: screen printing and subsequent firing. With better understanding and improvements in BNNN processing, we expect efficiencies of these cells to reach, or possibly exceed, the commercial cell efficiencies.
ARC, anti-reflection coating; BNNN, buried nanoparticle nanonetwork; CNT, carbon nanotubes; c-Si, crystalline silicon; ITO, indium tin oxide; NNN, nanoparticle nanonetwork; NP, nanoparticles; PSG, phosphorous silicate glass; PV, photovoltaics; PVP, polyvinylpyrrolidone; RTP, rapid thermal processor; TCE, transparent conductive electrodes; tSi, textured silicon
This work is supported by NSFC grant no. 51571094, Guangdong government funding with nos. of 2014B090915005, 2014A030313447, 2013KJCX0056, HD14CXY010, and 2014A010103024. K.K. thanks the Boston College Ignite Program for additional financial support. J.M. thanks the NSFC funding with number of 51431006. This work has been partial support from “PCSIRT” and “LOIT” in China and “China National Undergraduate Innovation Experiment Program”.
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