Fig. 3
From: Gate-Controlled WSe2 Transistors Using a Buried Triple-Gate Structure
Schematic band diagrams for electrostatically doped nFET, pFET, and TFET devices. a Illustration in the case of zero gate voltage in source, drain, and gate area. b Positive side-gate voltages create n-type regions in source and drain, c a positive side-gate voltage in source and a negative side-gate voltage in drain yield a tunnel FET device. d In the case of negative side-gate voltages, p-type source/drain electrodes are realized