Bi-layer Channel AZO/ZnO Thin Film Transistors Fabricated by Atomic Layer Deposition Technique
© The Author(s). 2017
Received: 30 December 2016
Accepted: 13 March 2017
Published: 24 March 2017
This letter demonstrates bi-layer channel Al-doped ZnO/ZnO thin film transistors (AZO/ZnO TFTs) via atomic layer deposition process at a relatively low temperature. The effects of annealing in oxygen atmosphere at different temperatures have also been investigated. The ALD bi-layer channel AZO/ZnO TFTs annealed in dry O2 at 300 °C exhibit a low leakage current of 2.5 × 10−13A, I on/I off ratio of 1.4 × 107, subthreshold swing (SS) of 0.23 V/decade, and high transmittance. The enhanced performance obtained from the bi-layer channel AZO/ZnO TFT devices is explained by the inserted AZO front channel layer playing the role of the mobility booster.
KeywordsThin-film transistor ALD Bi-layer channel ZnO AZO
Oxide thin-film-transistors (TFTs) have a growing need for the development of transparent displays, flexible electronics, and organic light-emitting diodes due to their excellent electrical and optical properties even at low deposition temperatures [1–3]. While a great number of various deposition techniques were reported on oxide thin films, the main deposition methods for oxide active layers in TFTs are based on physical vapor deposition (PVD), such as magnetron sputtering [4, 5], pulsed laser deposition , and evaporation . However, PVD technique has some problems such as non-reproducibility and non-uniformity for thin film composition in the growth of multicomponent oxide films, which hinder the mass production of the TFTs based on multicomponent oxides .
Atomic layer deposition (ALD) is a gas-phase thin film deposition technology characterized by the alternate exposure of chemical species with self-limiting surface reactions, providing extremely high uniformity, as well as thickness and composition control for the deposition of various oxides, nitrides, and sulfides [8–11]. Especially, ALD can produce high quality films at a relatively low temperature, making it compatible with both glass and plastic transparent substrates . Furthermore, oxide thin films processed by ALD are compatible not only with planar device architecture, but also with emerging 3D device architectures because ALD is capable of depositing conformal and uniform thin films on a wide range of substrates and geometries . The material development for active layers grown by ALD is a key issue for the fabrication of TFTs based on all ALD processes. Recently, Wang YH et al. reported the effects of post-annealing on the performance of ALD ZnO/Al2O3 thin-film transistors . Kwon S et al. reported that the processing temperatures have a huge impact on the characteristics of ALD ZnO thin film transistors . Ahn CH et al. reported Al doped ZnO channel layers TFTs with improved electrical stability fabricated by atomic layer deposition at a relatively low temperature . As advanced architecture for high performance TFTs, double channel devices have been widely investigated . In particular, double channel structure is a simple and an effective method for optimizing the carrier concentrations and channel resistivity, leading to higher on-state current and mobility . For example, Wang SL et al. reported high mobility indium oxide/gallium oxide bi-layer structures deposited by magnetron sputtering . Kim SI et al. reported high performance ITO/GIZO double active layer TFTs formed by a radio frequency magnetron sputtering . While double channel TFTs fabricated by sputtering were reported previously, the applications of the double-channel devices deposited by ALD have rarely been studied to date.
In this paper, we introduce the bi-layer channel AZO/ZnO TFTs fabricated using atomic layer deposition process at a relatively low temperature. The properties of ZnO, AZO, and bi-layer AZO/ZnO films were characterized by microstructure, crystal structure, and optical analysis techniques. The influences of annealing treatment for bi-layer channel AZO/ZnO TFTs have been discussed.
The single-layer ZnO and bi-layer AZO/ZnO films were deposited on SiO2 (50 nm)/p++ − Si substrates by atomic layer deposition (ALD) at 125 °C. Deionized water (DW), diethylzinc (DEZn), and trimethylaluminium (TMA) precursors were used as the sources for oxygen, aluminum, and zinc, respectively. N2 was employed as the purging gas with a flow rate of 20 sccm. The pulse/purge times for Zn, Al, and O sources are 40, 20, and 20 ms/25 s, respectively.
The crystal structure of ZnO, AZO, and bi-layer AZO/ZnO films was measured by X-ray diffraction (XRD, Rigako), and their surface morphology was evaluated by atomic force microscope (AFM). The optical transmittance spectra was analyzed to investigate the optical properties of ZnO, AZO, and bi-layer AZO/ZnO films. The electrical properties of the fabricated TFTs were measured using a semiconductor parameter analyzer (Agilent 4156C) at room temperature.
Results and Discussion
The extracted electrical parameters of bi-layer channel AZO/ZnO TFTs with different annealing treatments
I on/I off
V th (V)
I off (A)
N it (cm−2)
2.4 × 107
2.9 × 10−13
3.18 × 1012
Dry O2 at 300 °C
1.4 × 107
2.5 × 10−13
1.24 × 1012
Dry O2 at 250 °C
0.6 × 107
2.3 × 10−13
1.2 × 1012
Dry O2:Ar = 3:3 at 350 °C
0.6 × 107
1.0 × 10−14
0.77 × 1012
In summary, we have fabricated bi-layer channel AZO/ZnO TFTs via atomic layer deposition process at a relatively low temperature. The bi-layer channel AZO/ZnO TFTs exhibit a better performance than that of the single-layer ZnO TFTs. These results are attributed to the inserted AZO front channel layer serving as the mobility booster. In order to improve the SS of devices, bi-layer AZO/ZnO TFTs have been annealed in oxygen atmosphere at different temperatures. The results demonstrate that ALD bi-layer AZO/ZnO channel can be a promising candidate for the active layer of TFTs.
This work was supported in part by the National Basic Research Program of China (973 program, Grant No. 2013CBA01604) and by the National Natural Science Foundation of China (Grant No. 61275025).
HL designed the experiment with the assistance of DH and GC. LL and HL carried out the experiments and tested the devices. HL and JD analyzed the data and wrote the manuscript. DH, SZ, XZ, and YW supervised the work and finalized the manuscript. All authors read and approved the final manuscript.
HL received her B.S. degree from the University of Electronic Science and Technology of China, Chengdu, China in 2015. She is currently pursuing a M.S. degree at the Institute of Microelectronics, Peking University, Beijing, China. DH received his Ph.D. degree in solid-state electronics from Peking University, Beijing, China. He is currently an associate professor at the Institute of Microelectronics, Peking University. LL is currently pursuing a B.S. degree at the Institute of Microelectronics, Peking University, Beijing, China. JD received his M.S. degree in Shenzhen Graduate School of Peking University, Shenzhen, China in 2015 and B.S. degree from Xidian University, Xi’an, China in 2011. He is currently pursuing a Ph.D. degree at the Institute of Microelectronics, Peking University, Beijing, China. GC received his B.S. degree from the Institute of Microelectronics, Peking University, Beijing, China, in 2014. He is currently pursuing a M.S. degree at the Institute of Microelectronics, Peking University, Beijing, China. SZ received his Ph.D. degree from Peking University, Beijing, China. He is currently a professor at the Institute of Microelectronics, Peking University. XZ had a postdoctoral position at the Institute of Microelectronics, Peking University, Beijing, China in 1993. He is currently a professor at the Institute of Microelectronics, Peking University. YW received his Ph.D. degree from Tohoku University, Sendai, Japan. He is currently a professor at the Institute of Microelectronics, Peking University.
The authors declare that they have no competing interests.
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