Background

With the continuous development of integrated circuit, high-k materials have been extensively studied to substitute traditional SiO2 gate dielectrics in CMOS devices as a solution for the saturation of the leakage current and power consumption [1–3]. Lanthanum oxide (La2O3), aluminum oxide (Al2O3), yttrium oxide (Y2O3), hafnium oxide (HfO2), and zirconium oxides (ZrO2) have been tried to use as alternative gate dielectric materials [4–7]. Among them, La2O3 is regarded as a promising candidate due to the high dielectric constant (k ~ 27) and large band gap. Simultaneously, the accompanying problems also draw great attentions [8, 9].

The electrical properties of La2O3 and Al2O3 dielectric stacks have been studied by many researchers. Srikant Jayanti pointed out that significant improvement about charge trapping and leakage characteristics was obtained by using a La2O3 interface scavenging layer for Al2O3 interpoly dielectric [10]. Lee found that the hydration of La2O3 can be blocked by the Al2O3 in Al2O3/La2O3/Si (ALO structure) after the annealing treatment at 700 °C [11]. Researchers also revealed that the ultra-thin 0.5-nm Al2O3 inserted layer under the 4 nm LaAlO3 can reduce the EOT to 1.2 nm with optimized interface trap density. And compared with La2O3 and Al2O3 dielectric stacks (ALO or LAO structure), the lanthanum aluminate (LaAlO3) meets the thermal processing requirement better, since the added Al2O3 greatly improves the chemical stability and crystallization temperature [12, 13]. However, the electrical property difference between the La2O3/Al2O3 dielectric stacks and LaAlO3 have not been fully studied. In this paper, multilayer La2O3/Al2O3 stacks and LaAlO3 dielectric film were prepared by ALD reactor, and then, post-deposition annealing (PDA) was carried out at different temperatures. After the deposition of metal gate, the interfacial issues and electrical properties of the fabricated MIS structures were studied.

Methods

P-type Si (100) wafers with resistivity of 3–8 Ω cm were dipped in deionized water and diluted HF for 3 min, respectively, to remove the native oxide before deposition. Then La2O3/Al2O3 high-k stacks were deposited on Si wafers by ALD reactor (Picosun R-150, Espoo, Finland) in 300 °C. La(i-PrCp)3 and trinethyluminium (TMA) were used as precursors of La and Al, and O3 was used as oxidant. Besides, ultra-high purity nitrogen (N2, 99.999%) was employed as purge gas and carrier. The rapid thermal annealing (RTA) process was carried out at 600 and 800 °C in N2 ambient for 1 min after the deposition. A metal electrode with a diameter of 300 μm was fabricated by depositing 150 nm Al by the electron-beam evaporation through a shadow mask. In the end, the electrical properties including capacitance-voltage (C-V), conductance-voltage (G-V), and leakage current-voltage (I-V) characteristics were evaluated using an Agilent B1500A semiconductor parameter analyzer at the frequency of 100 kHz. X-ray photoelectron spectroscopy (XPS) was used to examine the bonding structures and chemical quantitative composition of the films. C1s peak from adventitious carbon at 284.6 eV [14] was used as an internal energy reference during the analysis.

Results and Discussion

The schematic structures and annealing temperatures are shown in Fig. 1 and Table 1. In Table 1, one-cycle La2O3 or Al2O3 came out from the reaction of a pulse of La or Al precursor and a pulse of oxidant O3. The samples S1 and S2 are multilayer La2O3/Al2O3 stacks with the same film structure and with 600 and 800 °C annealing temperatures, respectively, while the sample S3 is the LaAlO3 dielectric film annealed at 600 °C.

Fig. 1
figure 1

Schematic structures of multilayer La2O3/Al2O3 stack samples S1 and S2 and LaAlO3 sample S3

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Table 1 The structures and annealing temperatures of samples S1–S3
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Figures 2 and 3 show the C-V and G-V curves of samples S1, S2, and S3. The capacitors were swept forward (bias from negative to positive) and backward (bias from positive to negative) to check the C-V hysteresis at the frequency of 100 kHz. G-V curves were obtained simultaneously with the C-V curves. The ΔV FB is the flat band voltage difference of the C-V curve and its hysteresis. A clear decreasing of ΔV FB was observed with a higher annealing temperature with the same multilayer La2O3/Al2O3 stack structure. More apparently, sample S3 has a very small ΔV FB compared with S1 and S2.

Fig. 2
figure 2

C-V curves of samples S1–S3. ΔV FB were extracted from C-V curves

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Fig. 3
figure 3

G-V curves of samples S1–S3

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As we know, the trapped charges are responsible for the ΔV FB (hysteresis width) [15], and we assume that the two-dimensional distribution of traps near the interface contributes to the film capacitance. Then, the trapped charges density (N ot) can be expressed as in the following equation [16, 17]:

$$ {N}_{\mathrm{ot}}=\frac{\varDelta {V}_{\mathrm{FB}}{C}_{\mathrm{ox}}}{qA} $$
(1)
$$ {C}_{\mathrm{ox}}={C}_{\mathrm{ac}}\left[1+{\left(\frac{G_{\mathrm{ac}}}{\omega {C}_{\mathrm{ac}}}\right)}^2\right] $$
(2)

Where C ox is the insulator capacitance, q is the electron charge (1.602 × 10−19 C), A is the electrode area, C ac is the measured accumulation capacitance, ω is the angular frequency, and G ac is the conductance in accumulation region. By this model, the N ot is estimated to be 2.46 × 1012 cm−2, 1.54 × 1012 cm−2, and 6.20 × 1011 cm−2 for samples S1, S2, and S3 respectively.

The interface trap density (D it) value is another characteristic to evaluate the interface property of fabricated MIS capacitors. By Hill-Coleman single-frequency approximation, the D it can be expressed as [18]:

$$ {D}_{\mathrm{it}}=\frac{2}{qA}\frac{\frac{G_{\mathrm{ac}}}{\omega}}{\left[{\left(\frac{G_{\max }}{\omega {C}_{\mathrm{ox}}}\right)}^2+{\left(1-\frac{C_{\mathrm{c}}}{C_{\mathrm{ox}}}\right)}^2\right]} $$
(3)

Where G max is the maximum value of conductance, and C c is the corresponding capacitance of the gate voltage at which the G max is obtained. The D it of samples S1, S2, and S3 can be figured out as 1.24 × 1012 eV−1cm−2, 6.05 × 1011 eV−1cm−2, and 1.98 × 1012 eV−1cm−2 respectively. A higher D it of sample S1 than S2 can be attributed to the more recombination of dangling bonds at the high-k/Si interface for a higher annealing temperature. Compared with S1, sample S3 contains more La2O3/Al2O3 interfaces (we can regard the LaAlO3 dielectric film as a multilayer La2O3/Al2O3 stack which contains a very large number of plies), which means more interface trap.

So, a significant promotion in these two electrical properties can be obtained for a multilayer La2O3/Al2O3 stack at 800 °C annealing temperature compared with 600 °C. However, for LaAlO3 dielectric film, a promotion of N ot and a degradation of D it are obtained simultaneously. In a more comprehensive perspective, a better capacitance property are obtained from the LaAlO3 dielectric film, since the lower flat band voltage and less ΔV FB. And it is worth noting that a flat band voltage modulation can be carried out by manipulating the annealing temperature and the number of plies in multilayer La2O3/Al2O3 stack [19].

Figure 4 shows the leakage current density as a function of the applied gate voltage. S1 and S2 show a very similar leakage current, while S3 shows a 1 ~ 2 orders of magnitude larger leakage current with the same applied gate voltage. Then, XPS was employed to seek the explanation. Figure 5 shows the O1s XPS spectra of samples S1–S3, which was fitted with four peaks Si–O–Al (532.5 eV), Al–O–Al (531.5 eV), Al–O–La (530.9 eV), and La–O–La (528.75 eV). It is obvious that La–O–Al peaks become larger, while La–O–La, Al–O–Al, and Si–O–Al peaks become smaller from S1 to S3. Therefore, compared with S1 and S2, more La2O3 will appear at the interface of high-k/Si in sample S3. La2O3 has lower conduction band offset (CBO) and valence band offset (VBO) with respect to p-type Si substrate compared with Al2O3 (the CBO and VBO are about 2.3 and 2.6 eV for La2O3 and are about 2.8 and 4.9 eV for Al2O3) [20]. So, the increase of La2O3 in the high-k/Si interface will lead to the decrease of band offset as well as the increase of leakage current.

Fig. 4
figure 4

I-V curves of samples S1–S3

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Fig. 5
figure 5

O1s XPS spectra of samples S1–S3. The O1s spectra were fitted with four peaks (Si–O–Al, Al–O–Al, Al–O–La, and La–O–La)

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In addition, we notice that the sample S2 has a higher breakdown voltage than S1. It can be attributed to the lower trapped charges density, since structural defects lead to the possibility to generate a conduction path in gate dielectric [15].

Conclusions

In summary, the capacitance and leakage current properties for multilayer La2O3/Al2O3 stacks and LaAlO3 dielectric film have been studied systematically. A clear promotion of capacitance properties is observed for multilayer La2O3/Al2O3 stacks after PDA at 800 °C compared with that at 600 °C. As for LaAlO3 dielectric film, compared with multilayer La2O3/Al2O3 dielectric stacks, a promotion of N ot and a degradation of D it can be obtained at the same time. On the other hand, the LaAlO3 dielectric film presents a better leakage property which attributes to its higher CBO and VBO with respect to p-type Si substrate. And the breakdown behavior showed a clear improvement for the film with a higher annealing temperature for its less defects.