Open Access

Investigation of Bulk Traps by Conductance Method in the Deep Depletion Region of the Al2O3/GaN MOS Device

Nanoscale Research Letters201712:342

https://doi.org/10.1186/s11671-017-2111-z

Received: 22 February 2017

Accepted: 26 April 2017

Published: 10 May 2017

Abstract

Conductance method was employed to study the physics of traps (e.g., interface and bulk traps) in the Al2O3/GaN MOS devices. By featuring only one single peak in the parallel conductance (G p/ω) characteristics in the deep depletion region, one single-level bulk trap (E C-0.53 eV) uniformly distributed in GaN buffer was identified. While in the subthreshold region, the interface traps with continuous energy of E C-0.4~0.57 eV and density of 0.6~1.6 × 1012 cm−2 were extracted from the commonly observed multiple G p/ω peaks. This methodology can be used to investigate the traps in GaN buffer and facilitates making the distinction between bulk and interface traps.

Keywords

Al2O3/GaN MOS channel deviceConductance methodBuffer trapsInterface traps

Background

Owing to the superior properties of high electron mobility, high breakdown voltage, high-power density, low on-resistance, and high temperature operation capability, GaN heterojunction field-effect transistors (HFETs) have been considered as a promising solution for next-generation energy-efficient power electronics and attracted tremendous attention in the last two decades [1]. For power switching applications, the enhancement-mode (E-mode) transistors are highly preferred rather than the depletion-mode (D-mode) devices for the inherent fail-safe operation and simple gate driver circuitry. Despite the various technologies proposed to realize E-mode, GaN HFETs such as p-cap gate [2, 3], fluorine plasma ion implantation [4], and cascode technology [5], the MOSFET with partially or fully recessed gate is considered as a promising candidate because of its high-threshold voltage (V TH), large gate swing for improved fail-safe capability [6, 7], and low on-resistance [8]. Moreover, the MOS-gate is compatible with the mainstream gate driver ICs. However, the traps (e.g., interface and bulk traps) tarnish the advantages of GaN HFETs due to the stability and reliability issues such as V TH instability [9], drain lag or gate lag [10], and power slump. Besides the surface/interface traps, the GaN power HFETs’ performance such as the breakdown voltage and dynamic on-resistance could be substantially affected by the bulk traps in GaN buffer layer in high-voltage-switching applications [11, 12] since the high electric-field is prone to trigger the buffer traps for dynamic charging/discharging. Hence, it is of great significance to characterize the buffer traps of GaN MOS devices.

Bulk traps in GaN MOS devices have been studied by deep-level transient spectroscopy (DLTS) [13] and pulse measurement [14]. However, though the dynamic charge/discharge process of both bulk and interface trap-induced transient behavior may simultaneously appear in the same spectrum, extra effort is required to differentiate between the bulk and interface traps when using DLTS-like techniques and pulse measurement [15, 16]. On the other hand, the conductance method has been widely used to evaluate the interface traps in AlGaN/GaN MIS structures as well as GaN-based MIS structures [1719]. Moreover, it is possible to discriminate the bulk and interface traps in the conductance method by studying its bias dependence because the conductance loss is sensitive to the traps within a few kT/q around the Fermi level. In this letter, the conventional conductance method normally used to characterize the interface traps is employed to study the bulk traps (BT) in GaN buffer for the first time. Two trap-dominated regions were found in the Al2O3/GaN MOS structure with full barrier recess. In the deep depletion region, only one single Gp/ω peak is captured at the measured bias voltage ranging from −1 to 0 V, revealing the bulk traps with a single level in GaN buffer. The energy of the bulk trap was determined to be E C-0.53 eV. While in the subthreshold region, the interface traps with continuous energy levels that result in multiple Gp/ω peaks were observed within the measured bias range of 1.6~2.6 V. The energy levels were extracted to be in the range of 0.4 to 0.57 eV below GaN conduction band (CB).

Methods

The device structure used in this work is shown in Fig. 1. The Al2O3/GaN MOS device is fabricated on a commercial Al0.25Ga0.75N/GaN heterostructure grown on a 4-in Si (111) substrate by MOCVD. The AlGaN layer was fully recessed by using the low-damage hybrid recess technique. The detail fabrication process can be found in our previous work [7]. A 20-nm Al2O3 layer was deposited by atomic layer deposition (ALD) as the gate oxide. The conductance-frequency (G-f) and capacitance-voltage (C-V) characteristics were measured by an Agilent B1500A Semiconductor Device Analyzer equipped with a Cascade probe station. The frequency-dependent conductance measurements are shown within the range of 1 to 5 MHz.
Fig. 1

The schematic cross section of the Al2O3/GaN MOS device with full AlGaN-barrier removal

Results and Discussion

The 1/C 2 -V G and C-V G characteristics of the Al2O3/GaN MOS device measured at frequency of 1 MHz are shown in Fig. 2. A linear region was observed in the 1/C 2 -V G curve in the gate bias voltage range of 0–1.5 V in Fig. 2a. The flat band voltage (V FB) is determined to be 1.6 V by linear extrapolation of the 1/C 2 -V G curves to the intercept with the abscissa [20]. The background-doping concentration of GaN buffer N D was extracted to be 5 × 1014 cm3 from the linear slope. The good linear fitting suggests negligible trap states in the depletion region, since the linearity of the slope is strongly affected by the charge/discharge process of the traps [21, 22]. However, a decrease in slope implies the existence of residual trap states with the applied gate voltage both lower than 0 V and higher than 1.5 V, which corresponds to the deep depletion region and subthreshold region as highlighted in Fig. 2b.
Fig. 2

a 1/C 2 -V G characteristic on Al2O3/GaN MOS device measured at frequency of 1 MHz. The dashed dot line is the linear fitting of the linear part of the 1/C 2 -V G curve and the deviation from the linear slope as highlighted in the curves suggesting trap-dominated regions. b Two trap-dominated regions highlighted in the C-V G curve and marked with deep depletion and subthreshold region

In order to further differentiate the types of the traps (e.g., interface trap or bulk trap) and study the trap characteristics including the trap levels and densities, f-dependent conductance (Gp/ω) measurements were performed. The Gp/ω as a function of radial frequency (ω = 2πf) can be correlated to the traps density D T and trap response time τ T. For the case of bulk trap states with discrete energy level, Gp/ω is given by [23, 24]
$$ \frac{G_p}{\omega}=\frac{q\omega {\tau}_T{D}_T}{1+{\omega}_T^2{\tau}_T^2}, $$
(1)
whereas, for interface trap states with distributed energy levels, Gp/ω is given by
$$ \frac{G_p}{\omega}=\frac{q{ D}_T}{2\omega {\tau}_T} \ln \left(1+{\omega}_T^2{\tau}_T^2\right). $$
(2)
The maximum loss can be obtained when the trap states are in resonance with the applied AC signal for dynamic discharging/charging, which occurs when the trap states are exactly half-filled, i.e., when the energy level of the trap states crosses with the semiconductor Fermi level [24]. Consequently, the trap time constant corresponds to the maximum of Gp/ω and can be determined by setting the derivative ∂(Gp/ω)/∂(ωτT) to zero. By following the above two equations, the ωτ T is found to be 1 and 1.98 for bulk traps and interface traps, respectively. Thus, the Gp/ω peak frequency is associated with the trap energy level and the peak value is related to the trap density. The Gp/ω curves monotonically decrease with the increasing frequency without Gp/ω peaks at 0 V < VG < 1.5 V (see Fig. 3a) that corresponds to the observed linear regime shown in Fig. 2a, which reinforces the negligible charge/discharge processes of traps in this region. On the other hand, as shown in Fig. 3b, multiple peaks were observed in the Gp/ω curves while the device operated in the subthreshold region as the applied bias above the flat band voltage. In this region, the peaks steadily shift to higher frequencies with the increasing applied voltage, which is the typical Gp/ω characteristic indicating the presence of interface traps with continuous energy levels as commonly observed in conventional conductance measurements [1719, 23]. The Gp/ω characteristics in the deep depletion region (−1 V < V G < 0 V) are plotted in Fig. 3c which exhibits quite a difference compared with that observed in the subthreshold region. The Gp/ω curves within the measured bias range featured an identical profile with a single peak and the same Gp/ω peak value, which suggests the existence of trap state with only one single energy level while the electron emission rate of the trap state is irrelevant with V G. It is well known that bulk traps stem from the defects, and impurities are usually in a uniform-distribution throughout the bulky semiconductor. Correspondingly, the bulk traps are in discrete energy levels and capable of inducing the same loss peaks at the same frequency under various biases [24]. Hence, the Gp/ω characteristic with one peak observed in the deep depletion region reinforced that the bulk trap with one single level in GaN buffer layer was identified by conventional conductance measurement.
Fig. 3

Typical frequency-dependent parallel conductance (a) with 0 < V G < 1.5 V (b) with 1.5 V < V G < 2.6 V (subthreshold region) (c) with V G < 0 V (deep depletion region); the dots are the experimental data and the solid lines are fitting curves

The two types of traps (e.g., bulk and interface traps) can be easily discriminated by studying the bias-dependent conductance in different operation regions of the device as illustrated in the energy bandgap diagram of Al2O3/GaN MOS device in Fig. 4. The conductance method is sensitive to traps within a few kT/q around the Fermi level marked as the crossover point in Fig. 4. As shown in Fig. 4a, the single-level bulk traps are uniformly distributed in GaN buffer. The magnitude of Gp/ω peak originates from the bulk traps not varying with gate bias regardless of its spatial location. Meanwhile, the interface traps that cross over the Fermi level are much deeper in the GaN bandgap than the bulk trap at the given bias voltage. Therefore, the conductance loss was dominated by the dynamic response of the bulk traps rather than the interface traps in the deep depletion region. Further sweep up the bias voltage (e.g., 0 V < V G < 1.5 V), all of the bulk traps were filled with electrons as shown in Fig. 4b. On the other hand, the interface traps with a wide energy distribution may still capture the electrons. However, the conductance loss was not detected at the measured frequencies (e.g., 1 kHz–5 MHz) due to the extremely large time constant associated with the deep levels of the interface traps. Consequently, the 1/C 2 -V G plot exhibits a linear characteristic and the Gp/ω curves show a monotone property while 0 V < V G < 1.5 V as shown in Fig. 2a and Fig. 3a, respectively. In the subthreshold region (1.6 V < V G < 2.6 V), it can be seen from Fig. 4b that the conduction loss is solely contributed by the charging/discharging of the interface traps. Because the energy level of the interface traps that cross over the Fermi level are shallower in the subthreshold region, the relatively small time constant for dynamic charging/discharging can be detected as the multiple Gp/ω peaks measured in Fig. 3b.
Fig. 4

a The energy band diagram in depletion region to illustrate the conductance maximum loss induced by buffer traps irrelevant with V G. b Energy band bending in the subthreshold region to illustrate the conductance maximum loss induced by interface traps correlated with V G

By using Eq. (2), the fitting curves exhibit good agreement with the measured Gp/ω characteristics in the subthreshold region. The interface trap density and energy distribution profile were extracted and plotted versus the applied voltage in Fig. 5. The trap energy levels relative to the CB ∆E T as function of response time τ T given by the Shockley–Read–Hall statistics were extracted using the equation [14]:
$$ \varDelta {E}_T={k}_B T \ln \left({v}_{th}{\sigma}_n{N}_C{\tau}_T\right), $$
(3)
Fig. 5

Plots of D IT and the interface trap energy level relative to the CB (∆E IT= E C-E IT) for each applied gate voltage in the subthreshold region

where the capture cross section of the trap σ n = 4 × 10−13 cm−2, the electron thermal velocity v th =2.6 × 107 cm/s, the density of states at GaN CB N C = 2.2 × 1018 cm−3, the Boltzmann constant k B = 1.38 × 10−23J/K, and temperature T = 300 K were used [25]. The interface trap levels are in the range of 0.4 to 0.57 eV below GaN CB with D IT decreased from 1.6 × 1012 to 0.6 × 1012cm−2.

Similarly, the energy level and density of bu traps in GaN buffer also can be extracted by fitting the Gp/ω characteristics with Eqs. (1) and (3) as shown in Fig. 6. More importantly, as the measured Gp/ω characteristics exhibit an identical profile with only one single peak value at various bias voltages, the measured data were well fitted by a single curve instead of a series Gp/ω curves for the interface trap that feature a continuum energy-level distribution. Thus, single-level bulk traps with sheet density 1.5 × 1010 cm−2 and E BT = E C-0.53 eV (close to the reported Fe-induced level at 0.5 ± 0.1 eV below the GaN conduction band edge in GaN buffer [26, 27]) was extracted. Accordingly, the volume density N BT of the buffer trap can be obtained by dividing the sheet density by Debye length \( {L}_D=\sqrt{kT{\varepsilon}_S{\varepsilon}_0/\left({q}^2{N}_D\right)} \) as the depletion depth being in the same order of magnitude or smaller than the Debye length [28]. With the unintentional doping density N D  = 5 × 1014cm−3 extracted from the slope of the 1/C 2 -V G curve, N BT was estimated to be 9 × 1014cm−3.
Fig. 6

Experimental (dotted lines) and fitted (red circles) Gp/ω curves with gate biased in the deep depletion region

Conclusions

In conclusion, for the first time, the conventional conductance method was used to study the buffer traps in the Al2O3/GaN MOS device with full barrier removal. The bulk traps with a single energy level and uniformly distributed in GaN buffer that leads to a single Gp/ω peak were detected by f-dependent conductance measurements in the deep depletion region. On the other hand, the interface traps with wide energies were measured in the subthreshold region, which corresponds to the multiple Gp/ω peaks observed in the f-dependent conductance measurements. Due to the different f-dependent conductance response originating from the different energy and spatial distributions, the demonstrated approach is much easier to be used to investigate the physics of the bulk traps in GaN buffer.

Declarations

Funding

This work was supported in part by the National Natural Science Foundation of China under Project Nos. 61234006 and 61674024, and in part by the National Science and Technology Major Project 02 under Project No. 2013ZX02308-005, in part by the Natural Science Foundation of Guangdong Province, China, under project Grant No. 2015A030311016, in part by the Fundamental Research Funds for the Central Universities under project ZYGX2016J211 and in part by the opening project of State Key Laboratory of Electronic Thin Films and Integrated Devices under Grant KFJJ201609.

Authors’ contributions

YYS jointly conceived the study with ZJL. YYS, ABZ, LYZ, and YS performed the experiments. YYS and ZJL performed all the data analyses and wrote the original draft of the manuscript. QZ, WJC, and BZ reviewed and edited the manuscript. All authors reviewed the manuscript. All authors read and approved the final manuscript.

Competing interests

The authors declare that they have no competing interests.

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors’ Affiliations

(1)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China

References

  1. Ikeda N, Niiyama Y, Kambayashi H, Sato Y, Nomura T, Kato S, Yoshida S (2010) GaN power transistors on Si substrates for switching applications. Proc IEEE 98:1151–1161View ArticleGoogle Scholar
  2. Hu X, Simin G, Yang J, Asif Khan M, Gaska R, Shur MS (2000) Enhancement mode AIGaN/GaN HFET with selectively grown pn junction gate. Electron Lett 36:753–754View ArticleGoogle Scholar
  3. Uemoto Y, Hikita M, Ueno H, Matsuo H, Ishida H, Yanagihara M, Ueda T, Tanaka T, Ueda D (2006) A normally-off AlGaN/GaN transistor with RonA=2.6mΩcm2 and BVds=640V using conductivity modulation, in proc. Int. Electron Device Meeting (IEDM), San Francisco, CA., pp 1–4Google Scholar
  4. Cai Y, Zhou Y, Chen KJ, Lau KM (2005) High-performance enhancement -mode AlGaN/GaN HEMTs using fluoride-based plasma treatment. Electron Device Lett IEEE 26:435–437View ArticleGoogle Scholar
  5. Huang X, Liu Z, Li Q, Lee FC (2014) Evaluation and application of 600 V GaN HEMT in cascode structure. Trans Power Electron, IEEE 29:2453–2461View ArticleGoogle Scholar
  6. Zhou Q, Chen B, Jin Y, Huang S, Wei K, Liu X, Bao X, Mou J, Zhang B (2015) High-performance enhancement-mode Al2O3/AlGaN/GaN-on-Si MISFETs with 626 MW/cm2 figure of merit. Trans Electron Devices, IEEE 62:776–781View ArticleGoogle Scholar
  7. Zhou Q, Liu L, Zhang A, Chen B, Jin Y, Shi Y, Wang Z, Chen W, Zhang B (2016) 7.6 V threshold voltage high-performance normally-Off Al2O3/GaN MOSFET achieved by interface charge engineering. Electron Device Letters, IEEE 37:165–168View ArticleGoogle Scholar
  8. Wei J, Liu S, Li B, Tang X, Lu Y, Liu C, Hua M, Zhang Z, Tang G, Chen KJ (2015) Low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor. Electron Device Lett IEEE 36:1287–1290View ArticleGoogle Scholar
  9. Wang Y, Liang YC, Samudra GS, Huang H, Huang B, Huang S, Chang T, Huang C, Kuo W, Lo G (2015) 6.5 V high threshold voltage AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistor using multilayer fluorinated gate stack. Electron Device Lett IEEE 36:381–383View ArticleGoogle Scholar
  10. Binari SC, Klein PB, Kazior TE (2012) Trapping effects in GaN and SiC microwave FETs. Proc IEEE 90:1048–1058View ArticleGoogle Scholar
  11. Zhou C, Jiang Q, Huang S, Chen KJ (2012) Vertical leakage/breakdown mechanisms in AlGaN/GaN-on-Si devices. Electron Device Lett IEEE 33:1132–1134View ArticleGoogle Scholar
  12. Liao W, Chen Y, Chen Z, Chyi J, Hsin Y (2014) Gate leakage current induced trapping in AlGaN/GaN Schottky-gate HFETs and MISHFETs. Nanoscale Res Lett 9:474View ArticleGoogle Scholar
  13. Marso M, Wolter M, Javorka P, Kordos P, Lüth H (2003) Investigation of buffer traps in an AlGaN/GaN/Si high electron mobility transistor by backgating current deep level transient spectroscopy. Appl Phys Lett 82:633–635View ArticleGoogle Scholar
  14. Bisi D, Meneghini M, Santi C, Chini A, Dammann M, Brückner P, Mikulla M, Meneghesso G, Zanoni E (2013) Deep-level characterization in GaN HEMTs-part I: advantages and limitations of drain current transient measurements. Trans Electron Devices, IEEE 60:3166–3175View ArticleGoogle Scholar
  15. M.Ťapajna, J. L. Jimenez, and M. Kuball (2012) On the discrimination between bulk and surface traps in AlGaN/GaN HEMTs from trapping characteristics, Phys. Status Solidi A 209 :386–389Google Scholar
  16. Verzellesi G, Faqir M, Chini A, Fantini F, Meneghesso G, Zanoni E, Danesin F, Zanon F, Rampazzo F, Marino FA, Cavallini A, Castaldini A (2009) False surface-trap signatures induced by buffer traps in AlGaN-GaN HEMTs, in proc. IEEE Int. Rel. Phys. Symp., pp 732–735Google Scholar
  17. Kordoš P, Stoklas R, Gregušová D, Novák J (2009) Characterization of AlGaN/GaN metal-oxide-semiconductor field-effect transistors by frequency dependent conductance analysis. Appl Phys Lett 94:223512View ArticleGoogle Scholar
  18. Lu X, Yu K, Jiang H, Zhang A, Lau KM (2017) Study of interface traps in AlGaN/GaN MISHEMTs using LPCVD SiNx as gate dielectric. Trans Electron Devices, IEEE 64:824–831View ArticleGoogle Scholar
  19. M. Hua, Z. Zhang, J. Wei,J.Lei, G.Tang, K. Fu, Y. Cai, B.Zhang and K. J. Chen, (2016) Integration of LPCVD-SiNx gate dielectric with recessed-gate E-mode GaN MIS-FETs: toward high performance, high stability and long TDDB lifetime,, in Proc. Int. Electron Device Meeting (IEDM), San Francisco, CA, pp. 260–263Google Scholar
  20. Cardon F, Gomes WP (1978) On the determination of the flat-band potential of a semiconductor in contact with a metal or an electrolyte from the Mott-Schottky plot. J Phys D Appl Phys 11:L63–L67View ArticleGoogle Scholar
  21. Donnelly JP, Milnes AG (1967) The capacitance of p-n heterojunctions including the effects of interface states. IEEE Trans Electron Devices 14:63–68View ArticleGoogle Scholar
  22. Promros N, Yamashita K, Li C, Kawai K, Shaban M, Okajima T, Yoshitake T (2012) n-type nanocrystalline FeSi2/intrinsic Si/p-type Si heterojunction photodiodes fabricated by facing-target direct-current sputtering, Japanese. J of Appl Phys 51:021301Google Scholar
  23. Lehovec K (1966) Frequency dependence of the impedance of distributed surface states in MOS structures. Appl Phys Lett 8:48–50View ArticleGoogle Scholar
  24. Nicollian EH, Brews JR (1982) MOS physics and technology. John Wiley & Sons, New YorkGoogle Scholar
  25. Lehmann J, Leroux C, Charles M, Torres A, Morvan E, Blachier D, Ghibaudo G, Bano E, Reimbold G (2013) Sheet resistance measurement on AlGaN/GaN wafers and dispersion study. Microelectron Eng 109:334–337View ArticleGoogle Scholar
  26. Puzyrev YS, Schrimpf RD, Fleetwood DM, Pantelides ST (2015) Role of Fe impurity complexes in the degradation of GaN/AlGaN high-electron mobility transistors. Appl Phys Lett 106:053505View ArticleGoogle Scholar
  27. Wickramaratne D, Shen J, Dreyer CE, Engel M, Marsman M, Kresse G, Marcinkevicˇius S, Alkauskas A, Walle CGV (2016) Iron as a source of efficient Shockley-Read-Hall recombination in GaN. Appl Phys Lett 109:162107View ArticleGoogle Scholar
  28. Marco S, Uren MJ, Kuball M (2013) Iron-induced deep-level acceptor center in GaN/AlGaN high electron mobility transistors: energy level and cross section. Appl Phys Lett 102:073501View ArticleGoogle Scholar

Copyright

© The Author(s). 2017

Advertisement