Fig. 1From: A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process a 3D illustration of a 1T1R cell with STI-ReRAM right next to the n+ junction. b The corresponding TEM picture of resistive storage node composed of transitional metal oxides, formed between a specially placed contact and the n+ region of the select transistor. c LayoutBack to article page