Table 1 Nv-SRAM cell operation conditions
From: A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
Operation | BL | BLB | WL | VD |
|---|---|---|---|---|
Initialize RRAM | 0 V | 0 V | 0.75 V | 2.8 V |
Write SRAM | 1/0 | 0/1 | 1.1 V | 1.1 V (VDD) |
Write RRAM | 0 V | 0 V | 0 V | 2 V (VPP) |
NV data read | 0 V | 0 V | 0 V | 1.1 V (VDD) |