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Table 1 The comparison of reported work about β-Ga2O3 MOSFETs

From: Recent Advances in β-Ga2O3–Metal Contacts

Channel

Carrier density/cm−3

Device structure

Dielectric (method)

Process

S/D metal electrode

Flake [19]

5.5 × 1017

BG (D-M)

285-nm SiO2

Tube annealing

Ti/Au

Flake [88]

3 × 1017

BG (D-M)

300-nm SiO2

Ti/Au

Flake [89]

3 × 1017

TG (E-M)

42-nm HfO2(ALD)

Ti/Au

Flake [55]

3.7 × 1017

BG (D-M)

300-nm SiO2

RTP

Ti/Au

Flake [52]

2.7 × 1018

BG (D/E-M)

300-nm SiO2

Ar plasma bombardment

Ti/Al/Au

Flake [50]

8 × 1018

BG (D/E-M)

300-nm SiO2

Ar plasma bombardment

Ti/Al/Au

Sn-doped epilayer [12]

3 × 1017

TG (D-M)

20-nm Al2O3(ALD)

Si+ implantation(S/D) + RIE + RTP

Ti/Au

UID epilayer [57]

5 × 1019

FP (D-M)

20-nm Al2O3(ALD)

Si+ implantation (channel + S/D) + RIE + RTP

Ti/Au

Sn-doped epilayer [90]

6.34 × 1015

TG (D/E-M)

20-nm SiO2(ALD)

RIE + RTP

Ti/Au

Sn-doped epilayer [13]

4.8 × 1017

TG (E-M)

20-nm Al2O3(ALD)

RTP

Ti/Al/Ni/Au

Sn-doped epilayer [63]

2.3 × 1017

WG (E-M)

20-nm Al2O3(ALD)

RTP

Ti/Al/Ni/Au

UID epilayer [46]

< 4 × 1014

TG (E-M)

50-nm Al2O3(ALD)

Si+ implantation(S/D) + RIE + RTP

Ti/Au

Sn-doped epilayer [53]

2 × 1017

TG (D-M)

20-nm SiO2 (PEALD)

Spin-on-glass doping + RTP

Ti/Au

Ge-doped epilayer [21]

4 × 1017

TG (D-M)

20-nm Al2O3(ALD)

RTP

Ti/Al/Ni/Au

UID epilayer [64]

GR (E-M)

20-nm SiO2(ALD)

Highly doped epitaxial cap layer on S/D + RIE + RTP

Ti/Al/Ni/Au

  1. BG bottom gate, TG top gate, DG double gate, FP field plated, WG wrap gate, D-M depletion mode, E-M enhancement mode

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