Background

The system on chip (SoC) embedded memory market is currently in an era of tremendous growth, which requires the memory are capable of achieving faster operation, smaller cell size, and less power consumption [1,2,3,4,5,6]. Ferroelectric memory, one of the most promising candidates, has been reconsidered, due to the discovery of ferroelectric hafnium oxide in 2011 [7].

In the past decades, FeFET did not perform well in all these aspects includes low voltage requirements for memory operation, process step’s simplicity, and minimally complementary metal-oxide-semiconductor (CMOS) integration process and limited contamination concerns [8,9,10,11]. To address this, recently, tremendous investigation on 2D FeFET nonvolatile memory (NVM) has been performed based on various ferroelectric materials, including PbZrTiO3 (PZT), and [P(VDF-TrFE)] polymer [12,13,14,15,16,17,18], which is due to the promising properties of 2D material in “more than Moore era.” In the FeFET, the two stable spontaneous polarization states of a ferroelectric material incorporated into a transistor gate stack are utilized for data storage via the controllable threshold voltage enabled by applied shrunken P/E gate voltages. It is reported that the reproducible hysteresis behaviors, a high on/off ratio of 104, good retention properties up to 104 s, and stable switching operation have been achieved in PZT/MoS2 FeFET [19]. Noticeably, a maximum mobility of 625 cm2/V∙s, a large MW of 16 V for a ± 26 V gate—voltage range and a high on/off ratio of 8 × 105 have also been demonstrated by an n-type [P(VDF-TrFE)] polymer/MoS2 FeFET [15]. However, there are so many fundamental issues, which could prevent its practical application, like, CMOS compatibility, scaling capability, and the interface states between Fe and 2D material. Ferroelectric hafnium oxide, a kind of novel ferroelectric material, has excellent CMOS compatibility and scaling capability, which could serve for the advanced FeFET NVM at sub-5 nm technology node in the next 5-10 years [20]. Accordingly, a batch of HfO2-based dielectric stacks have been incorporated into 2D FeFETs, which are targeted to achieve negative capacitance field-effect transistors (NCFET) with steep ON/OFF switching via sub-60 mV/decade slope and hysteresis-free characteristics [21,22,23,24,25,26], Although mass experiments based on NC dielectric stack with alternate 2D channel materials have drawn fantastic conclusions, they highlighted the surge requirements to distinguish between NCFETs and FeFETs. There is still a lack of systematical investigation regarding the physics and viability of the device technology on one-transistor ferroelectric memory based on MoS2 and ferroelectric HZO.

In this work, a FeFET with a few-layered HZO MoS2 transistor has been proposed. It is capable of scaling the P/E voltage via the NC effect induced by gate stack engineering under a shrunken P/E voltage. We experimentally demonstrated that a counterclockwise MW of 0.1 V with sub-60 mV/decade slope has been achieved in HZO MoS2 FeFET, which can be attributed to local carrier density modulation in the 2D channel by fast flipping of ferroelectric dipole. We attributed the decreased hysteresis of the HZO/MoS2 FeFET as drain voltage increasing to negative drain-induced barrier lowering (DIBL) effect. In addition, it was also systematically studied retention, endurance characteristics, and the dependence of the threshold voltage on the drain voltage of HZO MoS2 FeFET, opening a feasible pathway to design HZO MoS2 FeFET NVM and its practical applications.

Methods

6 nm Hf1-xZrxO2 film and 2 nm Al2O3 was deposited on p+ Si substrate using ALD at 300 °C, with [(CH3)2N]4Hf(TDMAHf), [(CH3)2N]4Zr(TDMAZr), and H2O vapor as the Hf precursor, Zr precursor, and oxidant precursor, respectively. Subsequently, the substrate underwent rapid thermal annealing (RTA) at 450 °C for 30 s in N2 ambient. After that, few-layer MoS2 flakes were mechanically exfoliated and transferred onto the substrate. The diameter of p+ Si substrate used to deposit HZO (6 nm)/AI2O3 (2 nm) is 6 inches. We employed electron beam lithography (EBL) to pattern contact pads in poly(methyl methacrylate) (PMMA) A5 resist. The spin parameters, baking parameters, and imaging parameters are 500 r/min (9 s) + 4000 r/min (40 s), 170 °C (5 min), MIBK:IPA = 1:3 (15 s), respectively. Then, the source/drain electrodes (Ti/Au, 5/65 nm thickness) were evaporated using an e-beam evaporation (EBE) system and etched by acetone solution. After lift-off, the device was annealed at 300 °C for 2 h to enhance the contact. We carried out the electrical characterization of our fabricated MoS2/HZO field-effect transistors using a probe station with a micromanipulator. The back gate voltage (VGS) was applied on the p type heavily doped Si substrate. A semiconductor characterization system (PDA) was used to measure the source-drain voltage (VDS), the back gate voltage (VGS), and the source−drain current (IDS).

Results and Discussion

We prepared a few-layer MoS2 by mechanical exfoliation of bulk crystal and transferred the MoS2 nanoflake onto the 2 nm Al2O3/6 nm HZO/p+ Si substrate (see more details in the “Experimental” section). Figure 1a and b display a 3D schematic view and cross section of the HZO/MoS2 FeFET structure, respectively. A top-view scanning electron microscopy (SEM) image of the HZO/MoS2 FeFET is shown in Fig. 1c. The width and length of the MoS2 channel are 2 μm and 12 μm, respectively. As shown in Fig. 1d, the thickness of the MoS2 channel was confirmed using atomic force microscopy (AFM). The measured thickness of 1.57 nm indicates the presence of 4 layer of MoS2 [26].

Fig. 1
figure 1

Device structure and basic properties of the MoS2/HZO FeFET. a Three-dimensional schematic representation of the MoS2/HZO FeFET. b Schematic cross section of the MoS2/HZO FeFET. c Top-view SEM image of the fabricated MoS2/HZO FeFET with Ti/Au source/drain electrodes, HZO ferroelectric gate insulators, and MoS2 channels. d Height profile using contact-mode AFM along the red line in c, validating the height of the MoS2 channel.

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As shown in Fig. S1c and d, the elemental and bond composition of HZO was examined by the X-ray photoelectron (XPS) measurements. Peaks are found to be 19.05 eV, 17.6 eV, 185.5 eV, and 183.2 eV, which correspond to the Hf 4f5/2, Hf 4f7/2, Zr 3d3/2, and Zr 3d5/2, respectively [27]. The atomic concentration along the depth profile in Fig. S1e further confirms the distribution of the Al2O3/HZO/p+ Si tri-layer structure. All the above confirm that the HZO film grown via our atomic layer deposition (ALD) system is highly crystalline.

Before investigating the characterization of HZO/MoS2 FeFET, the ferroelectric behavior of the Au/2 nm Al2O3/6 nm HZO/p+ Si gate stack using polarization-voltage measurement is shown in Fig. 2a. Clearly, our fabricated 6 nm HZO/2 nm Al2O3 capacitors exhibit polarization-voltage hysteresis loops (measured at 1 kHz). Meanwhile, the remnant polarization Pr and the coercive voltage Vc increase with increasing the maximum sweeping voltage, implying the P-V hysteresis loops transform from minor loop to major loop. As the maximum sweeping voltage increases from 2 to 4 V, Pr reaches 0.66 μC/cm2, 0.86 μC/cm2, and 1.1 μC/cm2, respectively and Vc reaches 1.12 V, 1.9 V, and 2.04 V, respectively. Extracted Pr and Vc within 105 enduring DC sweeping cycles are shown in Fig. 2b and c. Obviously, significant wake-up and fatigue effects within 105 cycles are observed in the 6 nm HZO/2 nm Al2O3 capacitor. The wake-up and fatigue can be attributed to the diffusion and redistribution of the oxygen vacancies under the electric field. The fatigue effect is generally associated with charge trapping at the defect sites related to oxygen vacancies [28]. The hysteresis behaviors for the PRphase and butterfly-shaped loop for the PRampl using piezoresponse force microscopy (PFM) are displayed in Fig. S1b and c, indicating a polarization switching as a function of the sweep bias voltage. Considering different contact resistances between polarization-voltage measurement and piezo response-voltage measurement, the measured Vc in Fig. S1b and c is not so consistent with the values obtained in Fig. 2a.

Fig. 2
figure 2

a P-V hysteresis loops for the HZO (6 nm)/Al2O3 (2 nm) capacitor with different voltage sweeping ranges. Dependence of (b) Pr and cVc on cycling for the HZO (6 nm)/Al2O3 (2 nm) capacitor with ± 4 V/1 kHz cycling

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Additionally, it is observed that there is an increase in MW accompanied with the raised sweeping voltage range of gate voltage (VGS,range). Usually, poly-crystal HZO film exists as multi-domain status [29], and the coercive field distribution of these domains satisfies Gaussian distribution. Thus, there must be an increased dependence on the raised VGS,range. The coercive filed EC corresponds to the value of the external electric field which can reduce the remanent polarization to zero. Therefore, the VGS,range used to switch the polarization in the HZO film becomes larger with higher related coercive voltage VC. This is the reason why polarization-voltage loops of HZO film are extended with a larger VGS,range, which has been demonstrated in Fig. 2a. In other words, the enhanced polarization intensity and ferroelectric switching occur with the raised VGS,range, leading to the aforementioned phenomena of the extended counterclockwise MW produced by the increased VGS,range. At VGS,range = (−2, 2 V), the MW are almost vanished and nearly hysteresis-free characteristics emerge, which means the almost complete compensation between the effects of ferroelectric switching and charge trapping/de-trapping.

In order to further investigate the effect of ferroelectric switching, the VGS,range has been continuously increased to (−6, 6 V) and (−6.5, 6.5 V). The measured IDS-VGS curves of the HZO MoS2 FeFET at VGS,range = (−6, 6 V), and (−6.5, 6.5 V) are shown in Fig. 3a. Similarly, the counterclockwise memory window is increased with the extended VGS,range. At VGS,range = (−6.5, 6.5 V), the counterclockwise MW is above 4 V and the on/off ratio also increases to 107, which is due to the enhanced polarization switching under a larger external applied voltage. Generally, the mechanism underlying the hysteresis behaviors shown in the IDS-VGS curves during the bi-direction sweeping of VGS is threshold voltage shift, which can be modified by the predominant effects of polarization switching, that is NC effect [30,31,32], resulting in counterclockwise hysteresis. A further study of improved subthreshold characteristics was carried out in the other device under a shrunken VGS,range. The measured IDS-VGS and extracted point SS—IDS curves of the other device at VGS,range = (−3, 3 V) are plotted in Fig. 3b. It is demonstrated that at VGS,range = (−3, 3 V), HZO/MoS2 FeFET exhibits SSFor = 51.2 mV/decade and SSRev = 66.5 mV/decade, respectively. That is to say, the SS of sub-60 mV/decade and a MW of 0.48 V can be simultaneously achieved in HZO/MoS2 FeFET at room temperature, which will be a hint to distinguish between NCFET and FeFET.

Fig. 3
figure 3

The direct current (DC) test of the HZO/MoS2 FeFET when drain voltage (VDS) is 0.5 V. a The comparison between transfer curves with 6 V and 6.5 V as maximum of the back gate voltage. b Enlarged view of transfer curves at 0 to −2 V interval of VGS,range = (−3, 3 V). Point subthreshold slope (SS) as a function of drain current (IDS) of the HZO/MoS2 FeFET is (b) inset. The device exhibits SSFor = 51.2 mV/dec

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As it is known, in NCFET, the SS can be smaller than 60 mV/decade at room temperature due to the incorporation of the negative gate dielectric capacitance (Cins), which can be obtained via the negative slope segment of dP/dE < 0 induced by ferroelectric film, contributing to the gate stack factor (m) < 1. The mechanism underlying the NC effect [33] is the depolarization field generated by ferroelectric film [34,35,36,37,38]. It is experimentally reported that due to the incomplete screening at the interface of ferroelectric film [39], the residual polarization charge could produce an internal electrical field across ferroelectric film, which has the opposite direction with the externally applied voltage, leading to the re-distribution of the voltage across the gate stack and the amplified channel surface potential, named as “voltage amplification effect” [40,41,42]. The voltage amplification usually can be divided into two parts, the accelerated variation of channel surface potential and the subsequent boosted value, providing the steep ON/OFF switching and improved ION/IOFF, respectively. However, for FeFET, there is another story. According to the concept of capacitance matching between ferroelectric capacitance (CFE) and metal-oxide-semiconductor capacitance (CMOS) [43,44,45], when |CFE| > CMOS, the theoretical total capacitance (Ctotal) is positive and the system is stable, resulting in the same polarization behaviors during the bi-direction sweeping of VGS and the stable hysteresis-free NCFET. However, good matching resulting in improved SS and transconductance is very tricky to achieve, since both CMOS and CFE are very non-linear, bias dependent capacitors. Additionally, |CFE| > CMOS needs to be ensured for all the operating voltage range to avoid hysteresis. Instead, once |CFE| < CMOS, the theoretical Ctotal is negative and the system is unstable, a separated polarization behavior must occur during the bi-switching of VGS to keep the Ctotal positive, which could produce the counterclockwise hysteresis in FeFET for NVM application. Here, it is mentioned that the hysteretic behaviors is the subsequent effect of separated polarization switching, which means that the width of hysteresis window can be easily modified based on the concept of capacitance matching, such as, which can be manipulated by the variation of VDS. With an appropriate capacitance matching, even with a much shrunken VGS,range = (−3, 3 V), HZO/MoS2 FeFET still exhibits an obvious hysteresis window, and the steep switching of SSFor = 51.2 mV/dec at the same time, which further suggests the existence of the NC effect (ferroelectric polarization effect) in the subthreshold region as well. Although NCFET and FeFET are different, FeFET can also be adopted as logic devices with a comparable smaller MW, maintaining a deep sub-60 mV/dec SS, and a higher ION/IOFF ratio as well due to NC effect.

The impact of VDS on the width of MW has been carefully investigated. The IDS-VGS curves on logarithmic scales under different VDS are characterized in Fig. S3. It is exhibited that, at a fixed VGS,range = (−2, 2 V), the values of VGS extracted at IDS = 70 nA for the bi-directional sweeping of VGS all shift to the negative direction. Meanwhile, it is also demonstrated that the variation in forward sweeping of VGS is much more obvious over that of reverse sweeping, indicating the significant phenomena of negative DIBL. It should be noted that the negative DIBL effect always occurs with a NC effect [46, 47].

After the above direct current (DC) test of the HZO/MoS2 FeFET, we further carried out the measured MWs for different P/E VGS pulses with 10 ms width in Fig. 4a. MW is defined as the maximum change ΔVTH after P/E VGS pulses. During the pulsed VGS application, the other terminals were fixed to VS = VD = 0 V. For the read (R) operation, VGS was ranged from −1 V to 1 V with VD = 0.5 V and VS = 0 V. As shown in Fig. 4a, the extracted MWs become larger as P/E VGS pulses increase. When the imposed P/E VGS pulse is ± 3 V, the extracted MW is 0.1 V. When the imposed P/E VGS pulse is ± 5.5 V, the extracted MW is 0.275 V. Compared with the counterclockwise MWs of 4 V and 0.48 V in Fig. 3a and b, the extracted MWs after P/E VGS pulse is greatly reduced. This is possibly due to a higher density of trapping states induced by high humidity in the air [48]. Thus, the charge trapping/de-trapping mechanism is enhanced and the counterclockwise hysteresis loop is decreased eventually. Furthermore, we studied the cycling endurance and data retention of the HZO/MoS2 FeFET under P/E pulses with ± 5.5 V height in Fig. 4b. The program VGS pulse was 10 ms wide with VS = VD = 0 V. Figure 4b illustrates the measured MWs as a function of endurance cycles. The endurance cycle is formed by back-gate voltage periodic P/R/E/R pulses. Voltages applied to the back gate of the height of P, E, R were + 5.5 V, −5.5 V and 0 V, respectively. And the pulse width of P and E was 10 ms. Clearly, an MW of 0.3 V can be maintained without significant degradation after 103 P/E cycles. As the number of endurance cycle increased, the MW increases to 0.38 V after 10 cycles and then decreases back to 0.28 V after 600 cycles. The first broaden MW is called wake-up effect and the later shrunken MW is called fatigue effect. The wake-up effect corresponds to domain-wall de-pinning, leading to an increase of switchable polarization domains of the HZO film [49]. The fatigue effect corresponds to newly injected charges that pin the domain walls after great numbers of P/E cycles [50]. The data retention at room temperature is shown in Fig. 4c. Here, the MW degradation is negligible after 104 s. Therefore, a MW about 0.3 V can be expected to be sustainable over 10 years by the dotted extrapolation lines. As presented in Fig. 4d, the device is stable after 103 cycles under the P/E pulses with ± 3 V heights. The stability of the HZO/MoS2 FeFET shows a great perspective of applications in nonvolatile memory technology.

Fig. 4
figure 4

Memory performances of the HZO/MoS2 FeFET under P/E pulses. a Extracted MWs (MWs) under P/E pulses with ± 3 V, ± 4 V, ± 5 V, ± 5.5 V, and ± 6 V heights. b Endurance measurements under P/E pulse conditions. c Retention characteristic of the HZO/MoS2 FeFET. d Endurance of the HZO/MoS2 FeFET for 103 cycles under the P/E pulses with ± 3 V heights

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A comparison of figure-of-merit with FeFET-based devices combining MoS2 and ferroelectric gate dielectrics is provided in Table 1. Here, the device structure, remnant polarization, coercive electric field, hysteresis loop direction, MW, working voltage, endurance cycles, and retention time are listed. It is obvious that the device we fabricated exhibits the thinnest ferroelectric layer of 6 nm HZO and the lowest working voltage compared with other works [12,13,14,15,16,17,18], which is important for the future 2 nm or 3 nm process node of the back end of line (BEOL) memory. By scaling the thickness of the ferroelectric layer, a MW of about 0.1 V was achieved under a low working voltage of ± 3 V. Such a low working voltage can be attributed to the intrinsic characteristics of HZO layer compared with their counterparts, such as P(VDF-TrFE) or HfO2, which has much higher thickness. Furthermore, our device possesses lower remnant polarization Pr of 1.1 μC/cm2 compared with other reported FeFETs. The fast decay of retention loss in a FeFET is due to the existence of depolarization field Edep, which comes from the incomplete charge compensation due to the existence of the Al2O3 layer. Here, Edep is directly proportional to the remanent polarization Pr [51]. Thus, the high Ec and low Pr make the ratio Edep/Ec in MoS2/HZO FeFET much small, leading to a much small retention loss associated with the depolarization field effect. Although the retention performances of MoS2 FeFETs based on HZO and P(VDF-TrFE) are both around 104 s, the P(VDF-TrFE) film needs to be 150 nm [17].

Table 1 Comparison among the figure of merits of ferroelectric FETs based on MoS2.
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Conclusions

In conclusion, we investigated few-layered, MoS2-based ferroelectric memory transistor devices using an HZO back gate dielectric. Our fabricated devices exhibit counterclockwise hysteresis induced by ferroelectric polarization. In addition, our HZO/MoS2 ferroelectric memory transistor displayed excellent device performances: a high on/off current ratio of more than 107 and a counterclockwise MW of 0.1 V at a P/E voltage of 3 V, which has the endurance (103 cycles) and retention (104 s) performance. We thus believe that the results of our MoS2-based nonvolatile ferroelectric memory transistors exhibit promising perspectives for the future of 2D low-power non-volatile memory applications.