Introduction

In recent years, the evolution of semiconductor process technology continues to scale down the critical dimension in large-scale integrated circuits [1,2,3]. Advanced FinFET logic processes have become more complex for realizing more tightly packed transistors in multi-functional and more powerful Si chips. Reactive ion etching steps enhanced by plasma [4, 5] become inevitable in advanced nano-scale processes for achieving high aspect ratio structures which are essential for high packing density circuits [6]. For CMOS technology nodes beyond 45 nm, the transistor gates changed from the conventional poly-silicon gate with silicon dioxide to high-k metal gate stacks [7, 8]. This change makes the devices more susceptible to the plasma induced damage and might lead to unforeseen latent damages to the high-k dielectric layers. [9]. In state-of-art manufacturing processes of FinFETs, numerous RF plasma steps such as etching, deposition and cleaning processes are inevitable, which create higher frequencies of plasma induced charging events [10]. Both positive and negative charging on metal structures may occur. As these charges flow through the conductive paths made of pre-existing metal lines, via and contacts, the undesirable discharging through vulnerable parts of the circuits, particularly through the transistor gate dielectric may lead to significant reliability concerns. For instance, in the dry etching step, scattering impinging ions and sputtered materials at the reaction surface cause more defects in the bulk fins [11, 12]. To avoid the plasma charging event leading to irreversible damage to circuits, design rules that limit the size of metal structures are given. Another example of alleviating PID includes using protective diodes, which could shunt the plasma charging current away from sensitive circuits [13]. The introduction of In-Situ Steam Generation (ISSG) gate oxide reported improving its tolerance for plasma damage [14]. Furthermore, trimming the chamber and modifying PECVD-Ti deposition process were also found to alleviated plasma induced damage [15]. Most of these methods however result in undesirable limitations on circuit design flexibility or processing tradeoffs.

Conventionally, on-wafer test patterns have been used to monitor the plasma induced damage (PID) levels [16]. The most common and widely used parameter for monitoring on-wafer PID is the time-to-breakdown (TDDB) characteristics of the transistor gates with large antenna structures. The latent damage on gate dielectrics can be revealed by measuring the degradation of the gate dielectric layer under voltage or current stress tests. Hence, these patterns are not able to provide real-time feedback on the plasma processes [17]. In our previous works, an on-wafer plasma induced charging effect detector is demonstrated in advanced FinFET technologies. The PID detector uses capacitive coupling structure to induce a response on the floating gate [18,19,20]. Therefore, there is no damage to the gate dielectric layer as it does in a conventional PID detector. On these new detectors, one measures the shifting I–V curves to find out both the intensity, duration as well as polarity of charges on the antenna gate. It is found that these detectors may subject to saturation effect as the plasma intensity at certain recording sites exceeds critical levels. To extend the dynamic range of the PID detector, new antenna gate designs have been investigated in this work, where widening of the sensing ranges is successfully demonstrated.

Methods

The 3D schematic of plasma induced damage (PID) detector with a parasitic capacitor connected to the antenna node is shown in Fig. 1a. Differing from PID monitoring structure, this detector utilizes a long contact slot to couple the antenna voltage on the floating gate. The cross-sectional TEM photograph is shown in Fig. 1b. As shown in the figure, contact slots which collect charges are capacitively coupled to floating gate.

Fig. 1
figure 1

a The 3D illustrations of previously reported in-situ PID detector and the antenna capacitor is highlighting in this structure. b The TEM photo of PID detector, where the gate length of this detector is 140 nm

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Figure 2 compares the recorded threshold voltage distributions from these detectors across a 12-inches wafer. The negative threshold voltage shift indicates that negative charges were collected on the antenna, drawing positive charges into floating gate, resulting in negative threshold voltage shifts. It is found that as the antenna area increases, the rising total capacitance leads to lowering of the overall antenna voltages, hence, smaller the shift in Vt.

Fig. 2
figure 2

Threshold voltage range of samples with different size of antenna, and the corresponding total capacitance on the antenna

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Here, in Fig. 3a, the flow chart explaining the basic operation principles of the PID detector is outlined. As the plasma charge (QAnt) are collected on the antenna, the potential of the antenna gate, VAnt, varies. VAnt is then coupled to the floating gate (FG), promoting the tunneling of electrons either into or out of FG. After plasma processes, Vt of these detectors may become more negative or more positive based on the polarity of QAnt. Vt can be calculated by the FN tunneling current model with the parameter listed in Fig. 3b.

Fig. 3
figure 3

a The flow chart from plasma charges (QAnt) collected on the antenna to shift Vt. Based on the FN tunneling model, ΔVt can be calculated. b The list of parameters with its definitions

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Figure 4 illustrates all the possible capacitance on the FG-based PID detector. From Fig. 5, it is found that as the antenna area increases, ΔVt tends to saturate. As VAnt reaches the maximum levels, QAnt starts to leak out when the voltage level is too high. To avoid the plasma flux level exceeding the detector limitation, the antenna capacitance is deliberately increased by adding loading capacitors which could reduce the proportion of antenna capacitance in the total capacitance.

Fig. 4
figure 4

Composition of capacitance on the antenna structure with the additional loading capacitor, which is designed to modify the sensitivity of the PID detectors. Where CP is the overall parasitic capacitance on the floating gate

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Fig. 5
figure 5

Both the threshold voltage level as well as projected antenna voltage level saturates on patterns with increased antenna area

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Figure 6a shows the 2D structure of the previously reported in-situ PID detector, and three structures of realizing additional capacitors are presented. They are MOM capacitors, which use the larger overlap area of metal layers to increase the total capacitance in Fig. 6b, STI capacitors, which increase the capacitance by adjusting the length of the metal gate in Fig. 6c, and sidewall capacitors, which use the overlap area of metal gate and contact to form additional capacitor Fig. 6d.

Fig. 6
figure 6

Cross sectional illustration of a the in-situ PID detector, and those with a loading additional capacitor realized by b MOM, c STI, and d sidewall, respectively

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Experimental results and discussion

Figure 7 compares the total capacitance versus antenna ratios when different types of loading capacitors are added. The total capacitance is dominated by the antenna capacitance when the antenna ratio is greater than 1 K.

Fig. 7
figure 7

Comparison of total capacitance versus antenna ratios as the three types of loading capacitors are added

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When the added loading capacitance become comparable to the antenna capacitance, total capacitance could then be affected by the loading capacitors. Since the maximum amount of charges collected by the antenna is fixed; by increasing total capacitance, ΔV is expected decreased, according to ΔQ = CΔV. Thus, the sensitivity of the detection range could be suppressed, preventing saturation effect when plasma charging level exceed its original limits. Drain current characteristics for devices of AR = 10 with different STI capacitors are compared in Fig. 8. When a larger loading capacitor is added, the percentage of antenna capacitance in total capacitance is reduced. Under the same plasma charging flux, the total plasma charges after a period is proportional to the antenna area. Hence, when overall capacitance increases, VAnt is expected to be lowered, allowing for the detection of high plasma flux levels. As shown in Fig. 8, smaller shifts are found on the I–V curves for the samples with additional loading capacitors.

Fig. 8
figure 8

I–V curve of different sizes of STI capacitor with AR = 10. When the external capacitance is larger, the I–V curve is closer to that of the reference cells

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Box charts of the threshold voltages measured from samples with AR = 1 K and different sizes of MOM, STI, and Sidewall capacitors are compared in Fig. 9 When the loading capacitance is increased, less threshold voltage shift is observed on average. In the experimental design, CL by STI structure is too small to show impact of the charging level. Comparison in Fig. 10 suggested that three ways of adding loading capacitors can also effectively reduce the average response to plasma charging. The additional loading capacitor can successfully expand the detection range of the PID detector, while the sensitivity of the detectors is reduced. For achieving wide-range detection of plasma charging level, a series of PID detectors with different level of CL can be designed in a 1-D array for detecting plasma charging levels on both the high and low end.

Fig. 9
figure 9

Threshold voltages measured on samples with different sizes of MOM, STI and Sidewall capacitors are compared. All devices have the same AR of 1 K

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Fig. 10
figure 10

Comparison of the average ΔVt versus CL implemented by the three types of capacitor structures, where ΔVt is defined as the Vt difference between a detector cell and the reference cell. Data suggest that reduced sensitivity can be obtained as CL increased

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Conclusions

This study investigates a new antenna gate design to extend the sensing range of plasma induced charging levels on the PID monitoring detectors. By adding a loading capacitor, high antenna gate voltage subject to charge leak can be prevented, allowing for a higher level of charging level to be registered on the PID detectors. This novel design effectively widens the detection range of plasma charging levels in advanced CMOS BEOL processes.