Ge N-Channel MOSFETs with ZrO₂ Dielectric Achieving Improved Mobility

Abstract

High-mobility Ge nMOSFETs with ZrO₂ gate dielectric are demonstrated and compared against transistors with different interfacial properties of ozone (O₃) treatment, O₃ post-treatment and without O₃ treatment. It is found that with O₃ treatment, the Ge nMOSFETs with ZrO₂ dielectric having a EOT of 0.83 nm obtain a peak effective electron mobility (μ_eff) of 682 cm²/Vs, which is higher than that of the Si universal mobility at the medium inversion charge density (Q_inv). On the other hand, the O₃ post-treatment with Al₂O₃ interfacial layer can provide dramatically enhanced-μ_eff, achieving about 50% μ_eff improvement as compared to the Si universal mobility at medium Q_inv of 5 × 10¹² cm⁻². These results indicate the potential utilization of ZrO₂ dielectric in high-performance Ge nMOSFETs.

Background

GERMANIUM (Ge) has exhibited advantages of higher carrier mobility and lower processing temperature compared with Si devices. These make Ge to be an alternative for applications of ultrascaled CMOS logic devices and thin-film transistors (TFTs) as top layer in three-dimensional integrated circuits [1,2,3]. In the past few years, great efforts have been focused on surface passivation, gate dielectric, and channel engineering for Ge p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), which have contributed to significant improvement in electrical performance for the p-channel devices.

But for Ge n-channel MOSFETs, low effective carrier mobility (μ_eff) caused by poor interfacial layer of gate stack strongly limits the performance of the devices. Various surface passivation techniques including Si passivation [1], plasma post-oxidation [4], and InAlP passivation [5] and several high-κ dielectrics including HfO₂, ZrO₂ [6,7,8], Y₂O₃ [9], and La₂O₃ [10] have been explored in Ge nMOSFETs to boost the electron μ_eff. It was demonstrated that ZrO₂ dielectric integrated with Ge channel can provide a robust interface due to that a GeO₂ interfacial layer can react and intermix with the ZrO₂ layer [7]. A decent hole μ_eff has been reported in Ge p-channel transistors [6,7,8], while there is still a lot of room for improvement in electron μ_eff for their counterparts.

In this work, Ge nMOSFETs with ZrO₂ gate dielectric are fabricated to achieve improved μ_eff over Si in the entire range of inversion charge density (Q_inv). Ge transistors obtain a 50% improvement in electron μ_eff compared to the Si universal mobility at a medium Q_inv of 5.0 × 10¹² cm⁻².

Experimental

The key process steps for fabricating Ge nMOSFETs on 4-inch p-Ge(001) wafers with a resistivity of 0.136–0.182 Ω cm are shown in Fig. 1a. The source/drain (S/D) regions were implanted with phosphorous ion at a dose of 1 × 10¹⁵ cm⁻² and an energy of 30 keV followed by dopant activation annealing at 600 °C. After the pre-gate cleaning, Ge wafers were loaded into an atomic layer deposition chamber for the formation of the gate dielectric layer(s): Al₂O₃/O₃ oxidation/ZrO₂, ZrO₂, or O₃ oxidation/ZrO₂ for wafers A, B, or C, respectively. For wafer A, 0.9 nm Al₂O₃ was used to protect the channel surface during O₃ oxidation. O₃ oxidation was carried out at 300 °C for 15 min for both wafers A and C. For all the wafers, the thickness of ZrO₂ was ~ 3.3 nm. Subsequently, TiN(100 nm) gate metal was deposited via physical reactive sputtering, and lithography patterning and reactive ion etching were used to form the gate electrode. After that, a 25-nm-thick Ni layer was deposited in S/D regions. Finally, the post-metallization annealing (PMA) at 350 °C for 30 s was carried out to form the Ni germanide and improve the interface quality. Schematic and microscope images of the fabricated transistor are shown in Fig. 1b, c, respectively.

Fig. 1

a Key process steps for fabricating Ge nMOSFETs. b Cross-sectional schematic and c microscope image of the fabricated devices

Figure 2a, b shows the high-resolution transmission electron microscope (HRTEM) images of the gate stacks on wafers A and B, respectively. The unified thickness of the Al₂O₃/GeO_x interfacial layer (IL) for wafer A is ~ 1.2 nm indicating the 0.2–0.3 nm GeO_x. For the device on wafer B, an ultrathin GeO_x IL was experimentally demonstrated [7].

Fig. 2

HRTEM images of a TiN//ZrO₂/Al₂O₃/GeO_x/Ge, b TiN/ ZrO₂/GeO_x/Ge stacks for the devices on wafers A and B, respectively

Results and Discussion

The measured capacitance (C) and the leakage current (J) characteristics for Ge MOS capacitors on wafers A, B, and C are measured and shown in Fig. 3a, b, respectively. The equivalent oxide thickness (EOT) of the devices on wafers A, B, and C is extracted to be 1.79, 0.59, and 0.83 nm, respectively. Assuming the GeO_x IL provides an extra EOT of ~ 0.25 nm for wafers A and C by comparing wafers B and C, the 3.3 nm ZrO₂ contributes an EOT of ~ 0.6 nm with κ value of ~ 21.8, which is consistent with the previous reported value of amorphous ZrO₂ [11].These derived results also confirm that the thickness in GeO_x IL on wafer B is negligible.

Fig. 3

a Measured C as a function of voltage V characteristics for Ge pMOS capacitors on wafers A, B, and C. b J versus V curves for the devices. c Benchmarking of J (extracted at V_FB ± 1 V) of the Ge MOS capacitors in this work against data obtained for similar bias conditions from the literature

The GeO_x/Al₂O₃ IL for wafer A and GeO_x IL for wafer C produces the EOT of ~ 1.2 and ~ 0.25 nm, respectively. The EOT of the devices can be further reduced by decreasing the IL thickness or improving the interface quality, and enhancing the permittivity of ZrO₂ with some surface passivation, e.g., NH₃/H₂ plasma treatment [6]. Figure 3c compares J versus EOT characteristics for the Ge nMOSFETs in this work against values for other reported Ge devices [5, 12,13,14,15,16,17]. It is also observed that the results are consistent with the reported Ge MOS with ultra-thin EOT following the same trends, indicating the difference of leakage current shown in Fig. 3b should be mainly attributable to the difference of EOT.

Figure 4a shows measured drain current (I_D) and source current (I_S) versus gate voltage (V_G) curves of Ge nMOSFETs from wafers A, B, and C. All transistors have a gate length L_G of 4 μm and a gate width W of 100 μm. The point subthreshold swing (SS), defined as dV_G/d(logI_D), as a function of I_D curves for the transistors in Fig. 4a is calculated and shown in Fig. 4b. It is clarified that the transistor on wafer A exhibits the degraded I_D leakage floor and SS compared to the devices on wafers B and C. Besides the increase in EOT in devices on wafer A would bring in the increment of SS, these phenomenon should be partly attributed to the fact that the device with the Al₂O₃ inserted layer has a higher density of interface traps (D_it) within the bandgap of the Ge channel in comparison with the wafers B and C.

Fig. 4

a Measured I_D and I_S versus V_GS curves of Ge nMOSFETs on wafers A, B, and C. b Point SS as a function of I_D for the transistors. c I_D–V_D characteristics show that the Ge nMOSFET on wafer A has a higher drive current compared to the devices on wafers B and C

Figure 4c shows the measured output characteristics, i.e., I_D–V_D curves for various values of gate overdrive |V_G–V_TH| of the devices demonstrating that the Ge transistor on wafer A achieves significantly improved drive current compared to the devices on wafers B and C. Here, V_TH is defined as V_GS corresponding to an I_D of 10⁻⁷ A/μm. Considering the identical conditions for S/D formation, the boosted I_DS for transistors on wafer A indicates the higher μ_eff [18,19,20,21]. The Al₂O₃ layer has not led to the degradation of D_it performance near the conduction band of the Ge channel.

Figure 5a shows the total resistance R_tot as a function of L_G for the Ge nMOSFETs with ZrO₂ dielectric with an L_G ranging from 2 to 10 µm. The values of R_tot are extracted at a gate overdrive of 0. 6 V and a V_D of 0.05 V. The S/D resistance R_SD of the transistors is extracted to be ~ 13.5 kΩ μm, utilizing the fitted lines intersecting at the y-axis. The similar R_SD is consistent with the identical process of PMA and S/D formation. The channel resistance R_CH values of the devices are obtained by the slope of the fitted lines, i.e., ΔR_tot/ΔL_G, which can be used for calculating the μ_eff characteristics of Ge nMOSFETs. To evaluate the interface quality, interface trap densities (D_it) were extracted by the following equation according to Hill’s method [17]:

$$D_{{{\text{it}}}} = \frac{{2G_{{{\text{m}}\max }} /\omega }}{{qA\left[ {\left( {\frac{{G_{{{\text{mmax}}}} }}{{\omega C_{{{\text{ox}}}} }}} \right) + \left( {1 - C_{{\text{m}}} /C_{{{\text{ox}}}} } \right)^{2} } \right]}}$$

where q is the electronic charge, A is the area of the capacitor, G_m,max is the maximum value of measured conductance, with its corresponding capacitance C_m, ω is the angular frequency, and C_ox is gate oxide capacitance. The D_it values are calculated to be 3.7, 3.2, and 2.3 × 10¹² eV⁻¹ cm⁻² for the devices on wafers A, B, and C, respectively.

It is known that the calculated values correspond to the midgap D_it. The device with Al₂O₃ IL on wafer A has a higher midgap D_it compared to the devices on wafers B and C. This is consistent with the results in Figs. 3a and 4a, and the higher midgap D_it gives rise to a larger depletion capacitance dispersion in wafer A causing a higher leakage current of I_DS in comparison with the other two wafers. Note the wafer A should have the lower D_it near the conduction bandgap due to its higher μ_eff over wafers B and C.

Fig. 5

a R_tot versus L_G curves for Ge nMOSFETs on wafers A, B, and C. The fitted line intersecting at the y-axis and the slope of linear fit lines are utilized to extract the R_SD and R_CH, respectively. b μ_eff for the Ge nMOSFETs in this work versus previously published results for unstrained Ge transistors. The devices on wafer A show the improved μ_eff than the Si universal mobility in the entire range of Q_inv

It is well known that μ_eff is the bottleneck for high drive current and transconductance in Ge nMOSFETs. Here, μ_eff can be calculated by $\mu_{{{\text{eff}}}} = 1/[WQ_{{{\text{inv}}}} (\Delta R_{{{\text{tot}}}} /\Delta L_{{\text{G}}} )]$, where ΔR_tot/ΔL_G is the slope of the R_tot versus L_G as shown in Fig. 5a. Q_inv can be obtained by integrating the measured C_inv–V_G curves. In Fig. 5b, we compare the μ_eff versus Q_inv of the Ge nMOSFETs on wafers A, B, and C with those reported previously in [18, 22,23,24,25]. The extracted peak μ_eff values of the transistors on wafers A and C are 795 and 682 cm²/V s, respectively, and that of Ge nMOSFETs on wafer B is 433 cm²/V s. Ge nMOSFETs with Al₂O₃ IL achieve a significantly improved μ_eff in comparison with the transistors on wafer B or C, the devices in [18, 22,23,24,25] in a high field, and Si universal mobility in the entire Q_inv range. At a Q_inv of 5 × 10¹² cm⁻², a 50% μ_eff enhancement is achieved in devices on wafer A as compared to the Si universal mobility. This demonstrates that by protecting the channel surface for preventing the intermixing of ZrO₂ and GeO_x using Al₂O₃, a high-quality interface between gate insulator and Ge is realized to boost the mobility characteristics, which is also reported in the previous studies of Ge MOSFETs with ultrathin EOT [26]. μ_eff in transistors on wafer C is higher than the Si universal at a Q_inv of 2.5 × 10¹² cm⁻², although it rapidly decays with the increase in Q_inv range. This indicates that the used O₃ oxidation before ZrO₂ deposition would improve the interfacial quality to some extent; however, it does not lead to enough flat channel surface to effectively suppress the surface roughness scattering of the carrier at high Q_inv due to the intermixing of ZrO₂ and GeO_x, since it is reported that the generation of oxygen vacancies during the intermixing would increase the short-range order (SRO) roughness [27]. Optimizing the O₃ oxidation process or reducing the Al₂O₃ IL thickness can make the Ge transistor achieve a reduced EOT while maintaining a higher μ_eff at the high Q_inv.

Conclusions

The impacts of gate dielectric structure and morphology on Ge nMOSFET electrical characteristics are investigated. An Al₂O₃/ZrO₂ gate dielectric provides for significantly-improved μ_eff as compared to the Si universal mobility. μ_eff can be improved by inserting an Al₂O₃ layer between the ZrO₂ and Ge channel, which, however, inevitably leads to a larger EOT. Al₂O₃-free Ge nMOSFETs with O₃ oxidation of the Ge surface prior to ZrO₂ deposition achieve a peak μ_eff of 682 cm²/V s which is higher than that of Si at the similar Q_inv.