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Fig. 1 | Nanoscale Research Letters

Fig. 1

From: Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Fig. 1

a Capacitance equivalent circuit with QS (bottom) and NQS (top) structure of MFIS geometry. b Formulated \(\hbox{d}Q_{{\rm fe}}/\hbox{d}t\) with respect to \(Q_{{\rm fe}}\). c Numerical (using L–K equation) and simulated (TCAD data) analyses of P–E relationship in the ferroelectric material at different ferroelectric thicknesses (\(t_{{\rm fe}}\)) [9, 12]. d Simulations are validated using the measurement data of a NC-TFET [6, 13]

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